Lines Matching refs:asm
113 class I<dag oops, dag iops, string asm, string operands, string cstr,
118 let AsmString = !strconcat(asm, operands);
1648 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands,
1650 : I<oops, iops, asm, operands, "", pattern> {
1656 class SimpleSystemI<bit L, dag iops, string asm, string operands,
1658 : BaseSystemI<L, (outs), iops, asm, operands, pattern> {
1663 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands,
1665 : BaseSystemI<L, oops, iops, asm, operands, pattern>,
1673 string asm, string operands, list<dag> pattern>
1674 : BaseSystemI<L, oops, iops, asm, operands, pattern>,
1686 class TMSystemI<bits<4> CRm, string asm, list<dag> pattern>
1688 (outs GPR64:$Rt), (ins), asm, "\t$Rt", pattern> {
1695 class RegInputSystemI<bits<4> CRm, bits<3> Op2, string asm,
1697 : RtSystemI<0, (outs), (ins GPR64:$Rt), asm, "\t$Rt", pattern> {
1704 class TMSystemINoOperand<bits<4> CRm, string asm, list<dag> pattern>
1705 : TMBaseSystemI<0b0, CRm, 0b011, (outs), (ins), asm, "", pattern> {
1710 class TMSystemException<bits<3> op1, string asm, list<dag> pattern>
1711 : I<(outs), (ins timm64_0_65535:$imm), asm, "\t$imm", "", pattern>,
1751 class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
1753 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
1761 class SystemNoOperands<bits<3> op2, string asm, list<dag> pattern = []>
1762 : SimpleSystemI<0, (ins), asm, "", pattern>,
1866 class PstateWriteSimple<dag iops, string asm, string operands>
1867 : SimpleSystemI<0, iops, asm, operands> {
1934 class SystemXtI<bit L, string asm>
1937 asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> {
1949 class SystemLXtI<bit L, string asm>
1952 asm, "\t$Rt, $op1, $Cn, $Cm, $op2"> {
1987 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
1989 : I<oops, iops, asm, operands, "", pattern>, Sched<[WriteBrReg]> {
1997 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
1998 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
2004 class SpecialReturn<bits<4> opc, string asm>
2005 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
2010 class RCPCLoad<bits<2> sz, string asm, RegisterClass RC>
2011 : I<(outs RC:$Rt), (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]", "", []>,
2021 class AuthBase<bits<1> M, dag oops, dag iops, string asm, string operands,
2023 : I<oops, iops, asm, operands, "", pattern>, Sched<[]> {
2031 class AuthBranchTwoOperands<bits<1> op, bits<1> M, string asm>
2032 : AuthBase<M, (outs), (ins GPR64:$Rn, GPR64sp:$Rm), asm, "\t$Rn, $Rm", []> {
2041 class AuthOneOperand<bits<3> opc, bits<1> M, string asm>
2042 : AuthBase<M, (outs), (ins GPR64:$Rn), asm, "\t$Rn", []> {
2050 class AuthReturn<bits<3> op, bits<1> M, string asm>
2051 : AuthBase<M, (outs), (ins), asm, "", []> {
2058 class BaseAuthLoad<bit M, bit W, dag oops, dag iops, string asm,
2060 : I<oops, iops, asm, operands, cstr, []>, Sched<[]> {
2078 multiclass AuthLoad<bit M, string asm, Operand opr> {
2081 asm, "\t$Rt, [$Rn, $offset]", "">;
2084 asm, "\t$Rt, [$Rn, $offset]!",
2087 def : InstAlias<asm # "\t$Rt, [$Rn]",
2090 def : InstAlias<asm # "\t$Rt, [$wback]!",
2144 class BaseCmpBranch<RegisterClass regtype, bit op, string asm, SDNode node>
2146 asm, "\t$Rt, $target", "",
2160 multiclass CmpBranch<bit op, string asm, SDNode node> {
2161 def W : BaseCmpBranch<GPR32, op, asm, node> {
2164 def X : BaseCmpBranch<GPR64, op, asm, node> {
2210 bit op, string asm, SDNode node>
2212 asm, "\t$Rt, $bit_off, $target", "",
2231 multiclass TestBranch<bit op, string asm, SDNode node> {
2232 def W : BaseTestBranch<GPR32, tbz_imm0_31_diag, op, asm, node> {
2236 def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> {
2241 def : InstAlias<asm # "\t$Rd, $imm, $target",
2265 class BImm<bit op, dag iops, string asm, list<dag> pattern>
2266 : I<(outs), iops, asm, "\t$addr", "", pattern>, Sched<[WriteBr]> {
2275 class BranchImm<bit op, string asm, list<dag> pattern>
2276 : BImm<op, (ins am_b_target:$addr), asm, pattern>;
2277 class CallImm<bit op, string asm, list<dag> pattern>
2278 : BImm<op, (ins am_bl_target:$addr), asm, pattern>;
2286 RegisterClass regtype, string asm,
2288 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
2305 multiclass OneOperandData<bits<6> opc, string asm,
2307 def Wr : BaseOneOperandData<0b0, 0b0, 0b00000, opc, GPR32, asm, node>;
2309 def Xr : BaseOneOperandData<0b1, 0b0, 0b00000, opc, GPR64, asm, node>;
2312 class OneWRegData<bits<6> opc, string asm, SDPatternOperator node>
2313 : BaseOneOperandData<0b0, 0b0, 0b00000, opc, GPR32, asm, node>;
2315 class OneXRegData<bits<6> opc, string asm, SDPatternOperator node>
2316 : BaseOneOperandData<0b1, 0b0, 0b00000, opc, GPR64, asm, node>;
2318 class SignAuthOneData<bits<3> opcode_prefix, bits<2> opcode, string asm,
2320 : I<(outs GPR64:$dst), (ins GPR64:$Rd, GPR64sp:$Rn), asm, "\t$Rd, $Rn",
2332 class SignAuthZero<bits<3> opcode_prefix, bits<2> opcode, string asm,
2334 : I<(outs GPR64:$dst), (ins GPR64:$Rd), asm, "\t$Rd", "$dst = $Rd",
2345 class SignAuthTwoOperand<bits<4> opc, string asm,
2348 asm, "\t$Rd, $Rn, $Rm", "",
2362 class ClearAuth<bits<1> data, string asm>
2363 : I<(outs GPR64:$Rd), (ins GPR64:$Rn), asm, "\t$Rd", "$Rd = $Rn", []>, Sched<[]> {
2373 class SignAuthFixedRegs<bits<5> opcode2, bits<6> opcode, string asm>
2374 : I<(outs), (ins), asm, "", "", []>,
2398 class SignAuthPCRel<bits<2> opc, string asm>
2399 : I<(outs), (ins am_pauth_pcrel:$label), asm, "\t$label", "", []>,
2409 class SignAuthOneReg<bits<5> opcode2, bits<6> opcode, string asm>
2410 : I<(outs), (ins GPR64:$Rn), asm, "\t$Rn", "", []>,
2423 class SignAuthReturnPCRel<bits<3> opc, bits<5> op2, string asm>
2424 : I<(outs), (ins am_pauth_pcrel:$label), asm, "\t$label", "", []>,
2433 class SignAuthReturnReg<bits<6> op3, string asm>
2434 : I<(outs), (ins GPR64common:$Rm), asm, "\t$Rm", "", []>,
2446 class BaseFlagManipulation<bit sf, bit sz, dag iops, string asm, string ops>
2447 : I<(outs), iops, asm, ops, "", []>,
2460 class FlagRotate<dag iops, string asm, string ops>
2461 : BaseFlagManipulation<0b1, 0b0, iops, asm, ops> {
2473 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
2476 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
2490 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
2492 : BaseBaseAddSubCarry<isSub, regtype, asm,
2495 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
2497 : BaseBaseAddSubCarry<isSub, regtype, asm,
2503 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
2505 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
2509 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
2528 string asm, SDPatternOperator OpNode,
2532 asm, "\t$Rd, $Rn, $Rm", "",
2547 class BaseDiv<bit size, bit isSigned, RegisterClass regtype, string asm,
2549 : BaseTwoOperandRegReg<size, 0b0, {0,0,0,0,1,?}, regtype, asm, OpNode> {
2553 multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
2554 def Wr : BaseDiv<0b0, isSigned, GPR32, asm, OpNode>,
2557 def Xr : BaseDiv<0b1, isSigned, GPR64, asm, OpNode>,
2561 class BaseShift<bit size, bits<2> shift_type, RegisterClass regtype, string asm,
2563 : BaseTwoOperandRegReg<size, 0b0, {0,0,1,0,?,?}, regtype, asm, OpNode>,
2568 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
2569 def Wr : BaseShift<0b0, shift_type, GPR32, asm>;
2571 def Xr : BaseShift<0b1, shift_type, GPR64, asm, OpNode>;
2595 class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
2596 : InstAlias<asm#"\t$dst, $src1, $src2",
2600 RegisterClass addtype, string asm,
2603 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
2617 multiclass MulAccum<bit isSub, string asm> {
2619 def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm, []>,
2624 def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm, []>,
2630 class WideMulAccum<bit isSub, bits<3> opc, string asm,
2632 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
2639 class MulHi<bits<3> opc, string asm, SDNode OpNode>
2641 asm, "\t$Rd, $Rn, $Rm", "",
2659 class MulAccumWAlias<string asm, Instruction inst>
2660 : InstAlias<asm#"\t$dst, $src1, $src2",
2662 class MulAccumXAlias<string asm, Instruction inst>
2663 : InstAlias<asm#"\t$dst, $src1, $src2",
2665 class WideMulAccumAlias<string asm, Instruction inst>
2666 : InstAlias<asm#"\t$dst, $src1, $src2",
2670 SDPatternOperator OpNode, string asm>
2672 asm, "\t$Rd, $Rn, $Rm", "",
2694 class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
2695 : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "",
2729 string asm>
2731 asm, "\t$Rd, $imm$shift", "", []>,
2745 multiclass MoveImmediate<bits<2> opc, string asm> {
2746 def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
2750 def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
2757 string asm>
2760 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
2774 multiclass InsertImmediate<bits<2> opc, string asm> {
2775 def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
2779 def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
2822 arith_shifted_reg shifted_regtype, string asm,
2825 asm, "\t$Rd, $Rn, $Rm_and_shift", "",
2847 string asm, SDPatternOperator OpNode>
2850 asm, "\t$Rd, $Rn, $Rm_and_extend", "",
2873 Operand ext_op, string asm>
2876 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
2896 class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
2899 : InstAlias<asm#"\t$dst, $src1, $src2",
3112 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
3115 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
3130 multiclass ExtractImm<string asm> {
3131 def Wrri : BaseExtractImm<GPR32, imm0_31, asm,
3139 def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
3154 RegisterClass regtype, Operand imm_type, string asm>
3156 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
3171 multiclass BitfieldImm<bits<2> opc, string asm> {
3172 def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
3179 def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
3187 RegisterClass regtype, Operand imm_type, string asm>
3190 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
3205 multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
3206 def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
3213 def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
3225 RegisterClass sregtype, Operand imm_type, string asm,
3228 asm, "\t$Rd, $Rn, $imm", "", pattern>,
3246 logical_shifted_reg shifted_regtype, string asm,
3249 asm, "\t$Rd, $Rn, $Rm_and_shift", "", pattern>,
3268 class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
3269 : InstAlias<asm#"\t$dst, $src1, $src2",
3448 class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
3450 asm, "\t$Rd, $Rn, $Rm, $cond", "",
3470 multiclass CondSelect<bit op, bits<2> op2, string asm> {
3471 def Wr : BaseCondSelect<op, op2, GPR32, asm> {
3474 def Xr : BaseCondSelect<op, op2, GPR64, asm> {
3479 class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
3482 asm, "\t$Rd, $Rn, $Rm, $cond", "",
3509 multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {
3510 def Wr : BaseCondSelectOp<op, op2, GPR32, asm, frag> {
3513 def Xr : BaseCondSelectOp<op, op2, GPR64, asm, frag> {
3600 string asm, list<dag> pattern>
3601 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
3620 Operand indextype, string asm, list<dag> pattern> {
3624 asm, pattern>,
3627 def : InstAlias<asm # "\t$Rt, [$Rn]",
3632 Operand indextype, string asm, list<dag> pattern> {
3636 asm, pattern>,
3639 def : InstAlias<asm # "\t$Rt, [$Rn]",
3649 Operand indextype, string asm, list<dag> pattern> {
3653 asm, pattern>,
3656 def : InstAlias<asm # "\t$Rt, [$Rn]",
3670 class PrefetchUI<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
3673 asm, pat>,
3691 class LoadLiteral<bits<2> opc, bit V, RegisterOperand regtype, string asm, list<dag> pat>
3693 asm, "\t$Rt, $label", "", pat>,
3706 class PrefetchLiteral<bits<2> opc, bit V, string asm, list<dag> pat>
3708 asm, "\t$Rt, $label", "", pat>,
3834 class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
3836 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
3856 class ROInstAlias<string asm, DAGOperand regtype, Instruction INST>
3857 : InstAlias<asm # "\t$Rt, [$Rn, $Rm]",
3861 string asm, ValueType Ty, SDPatternOperator loadop> {
3863 def roW : LoadStore8RO<sz, V, opc, asm,
3874 def roX : LoadStore8RO<sz, V, opc, asm,
3884 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
3888 string asm, ValueType Ty, SDPatternOperator storeop> {
3890 def roW : LoadStore8RO<sz, V, opc, asm, (outs),
3900 def roX : LoadStore8RO<sz, V, opc, asm, (outs),
3909 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
3912 class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
3914 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
3935 string asm, ValueType Ty, SDPatternOperator loadop> {
3937 def roW : LoadStore16RO<sz, V, opc, asm, (outs regtype:$Rt),
3947 def roX : LoadStore16RO<sz, V, opc, asm, (outs regtype:$Rt),
3956 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
3960 string asm, ValueType Ty, SDPatternOperator storeop> {
3962 def roW : LoadStore16RO<sz, V, opc, asm, (outs),
3972 def roX : LoadStore16RO<sz, V, opc, asm, (outs),
3981 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
3984 class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
3986 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
4007 string asm, ValueType Ty, SDPatternOperator loadop> {
4009 def roW : LoadStore32RO<sz, V, opc, asm, (outs regtype:$Rt),
4019 def roX : LoadStore32RO<sz, V, opc, asm, (outs regtype:$Rt),
4028 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4032 string asm, ValueType Ty, SDPatternOperator storeop> {
4034 def roW : LoadStore32RO<sz, V, opc, asm, (outs),
4044 def roX : LoadStore32RO<sz, V, opc, asm, (outs),
4053 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4056 class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
4058 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
4079 string asm, ValueType Ty, SDPatternOperator loadop> {
4081 def roW : LoadStore64RO<sz, V, opc, asm, (outs regtype:$Rt),
4091 def roX : LoadStore64RO<sz, V, opc, asm, (outs regtype:$Rt),
4100 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4104 string asm, ValueType Ty, SDPatternOperator storeop> {
4106 def roW : LoadStore64RO<sz, V, opc, asm, (outs),
4116 def roX : LoadStore64RO<sz, V, opc, asm, (outs),
4125 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4128 class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
4130 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
4151 string asm, ValueType Ty, SDPatternOperator loadop> {
4153 def roW : LoadStore128RO<sz, V, opc, asm, (outs regtype:$Rt),
4163 def roX : LoadStore128RO<sz, V, opc, asm, (outs regtype:$Rt),
4172 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4176 string asm> {
4178 def roW : LoadStore128RO<sz, V, opc, asm, (outs),
4186 def roX : LoadStore128RO<sz, V, opc, asm, (outs),
4193 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4198 string asm, list<dag> pat>
4199 : I<outs, ins, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat>,
4225 multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
4228 asm, [(AArch64Prefetch timm:$Rt,
4236 asm, [(AArch64Prefetch timm:$Rt,
4275 string asm, list<dag> pattern>
4276 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
4295 multiclass BaseLoadUnscaleV84<string asm, bits<2> sz, bits<2> opc,
4298 (ins GPR64sp:$Rn, simm9:$offset), asm, []>,
4303 def : InstAlias<asm # "\t$Rt, [$Rn]",
4307 multiclass BaseStoreUnscaleV84<string asm, bits<2> sz, bits<2> opc,
4311 asm, []>,
4316 def : InstAlias<asm # "\t$Rt, [$Rn]",
4321 string asm, list<dag> pattern> {
4324 (ins GPR64sp:$Rn, simm9:$offset), asm, pattern>,
4327 def : InstAlias<asm # "\t$Rt, [$Rn]",
4332 string asm, list<dag> pattern> {
4336 asm, pattern>,
4339 def : InstAlias<asm # "\t$Rt, [$Rn]",
4343 multiclass PrefetchUnscaled<bits<2> sz, bit V, bits<2> opc, string asm,
4348 asm, pat>,
4351 def : InstAlias<asm # "\t$Rt, [$Rn]",
4360 dag oops, dag iops, string asm>
4361 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", []> {
4380 RegisterClass regtype, string asm> {
4383 (ins GPR64sp:$Rn, simm9:$offset), asm>,
4386 def : InstAlias<asm # "\t$Rt, [$Rn]",
4391 RegisterClass regtype, string asm> {
4395 asm>,
4398 def : InstAlias<asm # "\t$Rt, [$Rn]",
4407 string asm, string cstr, list<dag> pat>
4408 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]!", cstr, pat> {
4429 string asm>
4432 (ins GPR64sp:$Rn, simm9:$offset), asm,
4438 string asm, SDPatternOperator storeop, ValueType Ty>
4442 asm, "$Rn = $wback,@earlyclobber $wback",
4453 string asm, string cstr, list<dag> pat>
4454 : I<oops, iops, asm, "\t$Rt, [$Rn], $offset", cstr, pat> {
4475 string asm>
4479 asm, "$Rn = $wback,@earlyclobber $wback", []>,
4484 string asm, SDPatternOperator storeop, ValueType Ty>
4488 asm, "$Rn = $wback,@earlyclobber $wback",
4502 string asm>
4503 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
4522 Operand indextype, string asm> {
4526 (ins GPR64sp:$Rn, indextype:$offset), asm>,
4529 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
4536 Operand indextype, string asm> {
4541 asm>,
4544 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
4551 string asm>
4552 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback,@earlyclobber $wback", []> {
4573 Operand indextype, string asm>
4576 (ins GPR64sp:$Rn, indextype:$offset), asm>,
4581 Operand indextype, string asm>
4585 asm>,
4592 string asm>
4593 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn], $offset", "$Rn = $wback,@earlyclobber $wback", []> {
4614 Operand idxtype, string asm>
4617 (ins GPR64sp:$Rn, idxtype:$offset), asm>,
4622 Operand idxtype, string asm>
4626 asm>,
4633 string asm>
4634 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
4653 Operand indextype, string asm> {
4657 (ins GPR64sp:$Rn, indextype:$offset), asm>,
4661 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
4667 Operand indextype, string asm> {
4672 asm>,
4675 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
4701 dag oops, dag iops, string asm, string operands>
4702 : I<oops, iops, asm, operands, "", []> {
4715 dag oops, dag iops, string asm, string operands>
4716 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
4732 RegisterClass regtype, string asm>
4734 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
4738 RegisterClass regtype, string asm>
4740 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
4744 RegisterClass regtype, string asm>
4747 (ins GPR64sp0:$Rn), asm,
4763 RegisterClass regtype, string asm>
4766 asm, "\t$Rt, [$Rn]">,
4771 RegisterClass regtype, string asm>
4774 asm, "\t$Ws, $Rt, [$Rn]">,
4788 RegisterClass regtype, string asm>
4792 asm, "\t$Ws, $Rt, $Rt2, [$Rn]">,
4883 class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm,
4885 : I<(outs), (ins timm32_0_65535:$imm), asm, "\t$imm", "", pattern>,
4899 class UDFType<bits<16> opc, string asm>
4901 asm, "\t$imm", "", []>,
4917 string asm, list<dag> pattern>
4919 asm, "\t$Rd, $Rn", "", pattern>,
4937 Operand immType, string asm, list<dag> pattern>
4939 asm, "\t$Rd, $Rn, $scale", "", pattern>,
4955 multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
4958 def UWHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR32, asm,
4965 def UXHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR64, asm,
4972 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
4978 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
4984 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
4990 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
4996 multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
5000 fixedpoint_f16_i32, asm,
5010 fixedpoint_f16_i64, asm,
5019 fixedpoint_f32_i32, asm,
5028 fixedpoint_f32_i64, asm,
5036 fixedpoint_f64_i32, asm,
5045 fixedpoint_f64_i64, asm,
5059 Operand immType, string asm, list<dag> pattern>
5061 asm, "\t$Rd, $Rn, $scale", "", pattern>,
5077 ValueType dvt, string asm, SDPatternOperator node>
5079 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
5092 multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
5094 def UWHri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR16, f16, asm, node> {
5100 def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
5105 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
5110 def UXHri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR16, f16, asm, node> {
5116 def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
5121 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
5127 def SWHri: BaseIntegerToFP<isUnsigned, GPR32, FPR16, fixedpoint_recip_f16_i32, asm,
5137 def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_recip_f32_i32, asm,
5146 def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_recip_f64_i32, asm,
5155 def SXHri: BaseIntegerToFP<isUnsigned, GPR64, FPR16, fixedpoint_recip_f16_i64, asm,
5164 def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_recip_f32_i64, asm,
5172 def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_recip_f64_i64, asm,
5188 string asm>
5189 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
5210 RegisterClass srcType, RegisterOperand dstType, string asm,
5212 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
5230 RegisterOperand srcType, RegisterClass dstType, string asm,
5232 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
5249 multiclass UnscaledConversion<string asm> {
5250 def WHr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR16, asm> {
5256 def XHr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR16, asm> {
5262 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
5267 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
5272 def HWr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR32, asm> {
5278 def HXr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR64, asm> {
5284 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
5289 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
5295 asm, ".d"> {
5301 asm, ".d"> {
5313 RegisterClass srcType, string asm, list<dag> pattern>
5314 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
5327 multiclass FPConversion<string asm> {
5329 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
5333 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
5337 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
5341 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
5345 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
5349 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
5359 ValueType vt, string asm, SDPatternOperator node>
5360 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
5373 multiclass SingleOperandFPData<bits<4> opcode, string asm,
5377 def Hr : BaseSingleOperandFPData<{0b00,opcode}, FPR16, f16, asm, node> {
5382 def Sr : BaseSingleOperandFPData<{0b00,opcode}, FPR32, f32, asm, node> {
5386 def Dr : BaseSingleOperandFPData<{0b00,opcode}, FPR64, f64, asm, node> {
5392 multiclass SingleOperandFPDataNoException<bits<4> opcode, string asm,
5394 : SingleOperandFPData<opcode, asm, node, 0>;
5397 multiclass SingleOperandFPNo16<bits<6> opcode, string asm,
5400 def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
5404 def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
5410 multiclass FRIntNNT<bits<2> opcode, string asm, SDPatternOperator node = null_frag> :
5411 SingleOperandFPNo16<{0b0100,opcode}, asm, node>;
5419 string asm, list<dag> pat>
5421 asm, "\t$Rd, $Rn, $Rm", "", pat>,
5435 multiclass TwoOperandFPData<bits<4> opcode, string asm,
5437 def Hrr : BaseTwoOperandFPData<opcode, FPR16, asm,
5444 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
5450 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
5457 multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm,
5459 def Hrr : BaseTwoOperandFPData<opcode, FPR16, asm,
5465 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
5470 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
5483 RegisterClass regtype, string asm, list<dag> pat>
5485 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
5500 multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
5502 def Hrrr : BaseThreeOperandFPData<isNegated, isSub, FPR16, asm,
5509 def Srrr : BaseThreeOperandFPData<isNegated, isSub, FPR32, asm,
5515 def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
5566 RegisterClass regtype, string asm,
5568 : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
5585 string asm, list<dag> pat>
5586 : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
5599 multiclass FPComparison<bit signalAllNans, string asm,
5602 def Hrr : BaseTwoOperandFPComparison<signalAllNans, FPR16, asm,
5608 def Hri : BaseOneOperandFPComparison<signalAllNans, FPR16, asm,
5614 def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
5619 def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
5624 def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
5629 def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
5690 class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
5692 asm, "\t$Rd, $Rn, $Rm, $cond", "",
5711 multiclass FPCondSelect<string asm> {
5713 def Hrrr : BaseFPCondSelect<FPR16, f16, asm> {
5718 def Srrr : BaseFPCondSelect<FPR32, f32, asm> {
5722 def Drrr : BaseFPCondSelect<FPR64, f64, asm> {
5732 class BaseFPMoveImmediate<RegisterClass regtype, Operand fpimmtype, string asm>
5733 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
5745 multiclass FPMoveImmediate<string asm> {
5746 def Hi : BaseFPMoveImmediate<FPR16, fpimm16, asm> {
5751 def Si : BaseFPMoveImmediate<FPR32, fpimm32, asm> {
5755 def Di : BaseFPMoveImmediate<FPR64, fpimm64, asm> {
5773 RegisterOperand regtype, string asm, string kind,
5775 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5796 RegisterOperand regtype, string asm, string kind,
5798 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
5859 multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
5862 asm, ".8b",
5865 asm, ".16b",
5868 asm, ".4h",
5871 asm, ".8h",
5874 asm, ".2s",
5877 asm, ".4s",
5880 asm, ".2d",
5903 multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm,
5906 asm, ".8b",
5909 asm, ".16b",
5912 asm, ".4h",
5915 asm, ".8h",
5918 asm, ".2s",
5921 asm, ".4s",
5925 multiclass SIMDThreeSameVectorBHSTied<bit U, bits<5> opc, string asm,
5928 asm, ".8b",
5932 asm, ".16b",
5936 asm, ".4h",
5940 asm, ".8h",
5944 asm, ".2s",
5948 asm, ".4s",
5954 multiclass SIMDThreeSameVectorB<bit U, bits<5> opc, string asm,
5957 asm, ".8b",
5960 asm, ".16b",
5968 string asm, SDPatternOperator OpNode> {
5971 asm, ".4h",
5974 asm, ".8h",
5978 asm, ".2s",
5981 asm, ".4s",
5984 asm, ".2d",
5990 string asm,
5994 asm, ".4h",
5997 asm, ".8h",
6001 asm, ".2s",
6004 asm, ".4s",
6007 asm, ".2d",
6013 string asm, SDPatternOperator OpNode> {
6016 asm, ".4h",
6020 asm, ".8h",
6025 asm, ".2s",
6029 asm, ".4s",
6033 asm, ".2d",
6040 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
6043 asm, ".4h",
6046 asm, ".8h",
6049 asm, ".2s",
6052 asm, ".4s",
6057 multiclass SIMDLogicalThreeVector<bit U, bits<2> size, string asm,
6060 asm, ".8b",
6063 asm, ".16b",
6082 string asm, SDPatternOperator OpNode = null_frag> {
6084 asm, ".8b",
6088 asm, ".16b",
6122 class BaseSIMDThreeSameVectorDot<bit Q, bit U, bits<2> sz, bits<4> opc, string asm,
6126 BaseSIMDThreeSameVectorTied<Q, U, {sz, 0b0}, {0b1, opc}, RegType, asm, kind1,
6131 let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2 # "}");
6134 multiclass SIMDThreeSameVectorDot<bit U, bit Mixed, string asm, SDPatternOperator OpNode> {
6135 def v8i8 : BaseSIMDThreeSameVectorDot<0, U, 0b10, {0b001, Mixed}, asm, ".2s", ".8b", V64,
6137 def v16i8 : BaseSIMDThreeSameVectorDot<1, U, 0b10, {0b001, Mixed}, asm, ".4s", ".16b", V128,
6145 class BaseSIMDThreeSameVectorFML<bit Q, bit U, bit b13, bits<3> size, string asm, string kind1,
6149 BaseSIMDThreeSameVectorTied<Q, U, size, 0b11101, RegType, asm, kind1,
6154 let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2 # "}");
6158 multiclass SIMDThreeSameVectorFML<bit U, bit b13, bits<3> size, string asm,
6160 def v4f16 : BaseSIMDThreeSameVectorFML<0, U, b13, size, asm, ".2s", ".2h", V64,
6162 def v8f16 : BaseSIMDThreeSameVectorFML<1, U, b13, size, asm, ".4s", ".4h", V128,
6166 multiclass SIMDThreeSameVectorMLA<bit Q, string asm>{
6167 def v8f16 : BaseSIMDThreeSameVectorDot<Q, 0b0, 0b11, 0b1111, asm, ".8h", ".16b",
6171 multiclass SIMDThreeSameVectorMLAL<bit Q, bits<2> sz, string asm>{
6172 def v4f32 : BaseSIMDThreeSameVectorDot<Q, 0b0, sz, 0b1000, asm, ".4s", ".16b",
6183 RegisterOperand regtype2, string asm,
6185 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, regtype2:$Rm), asm,
6206 multiclass SIMDThreeSameSizeVectorCvt<string asm> {
6207 def v8f8 : BaseSIMDThreeVectors<0b0, 0b0, 0b01, 0b1110, V64, V64, asm, ".8b",".4h">;
6208 def v16f8 : BaseSIMDThreeVectors<0b1, 0b0, 0b01, 0b1110, V128, V128, asm, ".16b", ".8h">;
6213 multiclass SIMDThreeVectorCvt<string asm> {
6214 def v8f8 : BaseSIMDThreeVectors<0b0, 0b0, 0b00, 0b1110, V64, V128, asm, ".8b", ".4s">;
6215 def 2v16f8 : BaseSIMDThreeSameVectorDot<0b1, 0b0, 0b00, 0b1110, asm#2, ".16b", ".4s",
6220 multiclass SIMDThreeSameVectorDOT2<string asm> {
6221 def v4f16 : BaseSIMDThreeSameVectorDot<0b0, 0b0, 0b01, 0b1111, asm, ".4h", ".8b",
6223 def v8f16 : BaseSIMDThreeSameVectorDot<0b1, 0b0, 0b01, 0b1111, asm, ".8h", ".16b",
6227 multiclass SIMDThreeSameVectorDOT4<string asm> {
6228 def v2f32 : BaseSIMDThreeSameVectorDot<0b0, 0b0, 0b00, 0b1111, asm, ".2s", ".8b",
6230 def v4f32 : BaseSIMDThreeSameVectorDot<0b1, 0b0, 0b00, 0b1111, asm, ".4s", ".16b",
6240 bits<2> size2, RegisterOperand regtype, string asm,
6242 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
6265 string asm, string dstkind, string srckind,
6267 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
6288 multiclass SIMDTwoVectorBHS<bit U, bits<5> opc, string asm,
6291 asm, ".8b", ".8b",
6294 asm, ".16b", ".16b",
6297 asm, ".4h", ".4h",
6300 asm, ".8h", ".8h",
6303 asm, ".2s", ".2s",
6306 asm, ".4s", ".4s",
6311 RegisterOperand regtype, string asm, string dstkind,
6313 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
6346 multiclass SIMDLongTwoVector<bit U, bits<5> opc, string asm,
6349 asm, ".4h", ".8b",
6352 asm, ".8h", ".16b",
6355 asm, ".2s", ".4h",
6358 asm, ".4s", ".8h",
6361 asm, ".1d", ".2s",
6364 asm, ".2d", ".4s",
6368 multiclass SIMDLongTwoVectorTied<bit U, bits<5> opc, string asm,
6371 asm, ".4h", ".8b",
6375 asm, ".8h", ".16b",
6379 asm, ".2s", ".4h",
6383 asm, ".4s", ".8h",
6387 asm, ".1d", ".2s",
6391 asm, ".2d", ".4s",
6397 multiclass SIMDTwoVectorBHSDTied<bit U, bits<5> opc, string asm,
6400 asm, ".8b", ".8b",
6403 asm, ".16b", ".16b",
6406 asm, ".4h", ".4h",
6409 asm, ".8h", ".8h",
6412 asm, ".2s", ".2s",
6415 asm, ".4s", ".4s",
6418 asm, ".2d", ".2d",
6422 multiclass SIMDTwoVectorBHSD<bit U, bits<5> opc, string asm,
6425 asm, ".8b", ".8b",
6428 asm, ".16b", ".16b",
6431 asm, ".4h", ".4h",
6434 asm, ".8h", ".8h",
6437 asm, ".2s", ".2s",
6440 asm, ".4s", ".4s",
6443 asm, ".2d", ".2d",
6449 multiclass SIMDTwoVectorB<bit U, bits<2> size, bits<5> opc, string asm,
6452 asm, ".8b", ".8b",
6455 asm, ".16b", ".16b",
6461 multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
6464 asm, ".8b", ".8b",
6467 asm, ".16b", ".16b",
6470 asm, ".4h", ".4h",
6473 asm, ".8h", ".8h",
6479 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
6485 asm, ".4h", ".4h",
6488 asm, ".8h", ".8h",
6492 asm, ".2s", ".2s",
6495 asm, ".4s", ".4s",
6498 asm, ".2d", ".2d",
6503 multiclass SIMDTwoVectorFPNoException<bit U, bit S, bits<5> opc, string asm,
6505 : SIMDTwoVectorFP<U, S, opc, asm, OpNode, 0>;
6509 multiclass SIMDTwoVectorSD<bit U, bits<5> opc, string asm,
6513 asm, ".2s", ".2s",
6516 asm, ".4s", ".4s",
6519 asm, ".2d", ".2d",
6523 multiclass FRIntNNTVector<bit U, bit op, string asm,
6525 SIMDTwoVectorSD<U, {0b1111,op}, asm, OpNode>;
6528 multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
6531 asm, ".2s", ".2s",
6534 asm, ".4s", ".4s",
6539 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
6543 asm, ".4h", ".4h",
6546 asm, ".8h", ".8h",
6550 asm, ".2s", ".2s",
6553 asm, ".4s", ".4s",
6556 asm, ".2d", ".2d",
6561 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
6565 asm, ".4h", ".4h",
6568 asm, ".8h", ".8h",
6572 asm, ".2s", ".2s",
6575 asm, ".4s", ".4s",
6578 asm, ".2d", ".2d",
6585 string asm, string outkind, string inkind,
6587 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
6608 string asm, string outkind, string inkind,
6610 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
6628 multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
6631 asm, ".8b", ".8h",
6634 asm#"2", ".16b", ".8h", []>;
6636 asm, ".4h", ".4s",
6639 asm#"2", ".8h", ".4s", []>;
6641 asm, ".2s", ".2d",
6644 asm#"2", ".4s", ".2d", []>;
6660 multiclass SIMDMixedTwoVectorFP8<bits<2>sz, string asm> {
6662 asm, ".8h", ".8b", []>;
6664 asm#2, ".8h", ".16b", []>;
6668 bits<5> opcode, RegisterOperand regtype, string asm,
6671 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
6693 multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
6696 asm, ".8b", "0",
6699 asm, ".16b", "0",
6702 asm, ".4h", "0",
6705 asm, ".8h", "0",
6708 asm, ".2s", "0",
6711 asm, ".4s", "0",
6714 asm, ".2d", "0",
6720 string asm, SDNode OpNode> {
6725 asm, ".4h", "0.0",
6728 asm, ".8h", "0.0",
6732 asm, ".2s", "0.0",
6735 asm, ".4s", "0.0",
6738 asm, ".2d", "0.0",
6743 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
6745 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0",
6748 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
6750 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
6752 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
6755 def : InstAlias<asm # ".4h\t$Vd, $Vn, #0",
6757 def : InstAlias<asm # ".8h\t$Vd, $Vn, #0",
6760 def : InstAlias<asm # ".2s\t$Vd, $Vn, #0",
6762 def : InstAlias<asm # ".4s\t$Vd, $Vn, #0",
6764 def : InstAlias<asm # ".2d\t$Vd, $Vn, #0",
6771 string asm, string VdTy, string VnTy,
6773 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
6793 string asm, string VdTy, string VnTy,
6795 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
6812 multiclass SIMDFPWidenTwoVector<bit U, bit S, bits<5> opc, string asm> {
6814 asm, ".4s", ".4h", []>;
6816 asm#"2", ".4s", ".8h", []>;
6818 asm, ".2d", ".2s", []>;
6820 asm#"2", ".2d", ".4s", []>;
6823 multiclass SIMDFPNarrowTwoVector<bit U, bit S, bits<5> opc, string asm> {
6825 asm, ".4h", ".4s", []>;
6827 asm#"2", ".8h", ".4s", []>;
6829 asm, ".2s", ".2d", []>;
6831 asm#"2", ".4s", ".2d", []>;
6834 multiclass SIMDFPInexactCvtTwoVector<bit U, bit S, bits<5> opc, string asm,
6837 asm, ".2s", ".2d",
6840 asm#"2", ".4s", ".2d", []>;
6854 RegisterOperand intype2, string asm,
6857 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
6880 RegisterOperand intype2, string asm,
6883 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
6907 multiclass SIMDNarrowThreeVectorBHS<bit U, bits<4> opc, string asm,
6911 asm, ".8b", ".8h", ".8h",
6915 asm#"2", ".16b", ".8h", ".8h",
6919 asm, ".4h", ".4s", ".4s",
6923 asm#"2", ".8h", ".4s", ".4s",
6927 asm, ".2s", ".2d", ".2d",
6931 asm#"2", ".4s", ".2d", ".2d",
6954 multiclass SIMDDifferentThreeVectorBD<bit U, bits<4> opc, string asm,
6958 asm, ".8h", ".8b", ".8b",
6962 asm#"2", ".8h", ".16b", ".16b", []>;
6966 asm, ".1q", ".1d", ".1d",
6970 asm#"2", ".1q", ".2d", ".2d",
6980 multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
6984 asm, ".4s", ".4h", ".4h",
6988 asm#"2", ".4s", ".8h", ".8h",
6993 asm, ".2d", ".2s", ".2s",
6997 asm#"2", ".2d", ".4s", ".4s",
7002 multiclass SIMDLongThreeVectorBHSabdl<bit U, bits<4> opc, string asm,
7006 asm, ".8h", ".8b", ".8b",
7011 asm#"2", ".8h", ".16b", ".16b",
7017 asm, ".4s", ".4h", ".4h",
7022 asm#"2", ".4s", ".8h", ".8h",
7028 asm, ".2d", ".2s", ".2s",
7033 asm#"2", ".2d", ".4s", ".4s",
7040 string asm,
7044 asm, ".8h", ".8b", ".8b",
7050 asm#"2", ".8h", ".16b", ".16b",
7057 asm, ".4s", ".4h", ".4h",
7063 asm#"2", ".4s", ".8h", ".8h",
7070 asm, ".2d", ".2s", ".2s",
7076 asm#"2", ".2d", ".4s", ".4s",
7083 multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
7087 asm, ".8h", ".8b", ".8b",
7091 asm#"2", ".8h", ".16b", ".16b",
7096 asm, ".4s", ".4h", ".4h",
7100 asm#"2", ".4s", ".8h", ".8h",
7105 asm, ".2d", ".2s", ".2s",
7109 asm#"2", ".2d", ".4s", ".4s",
7115 string asm,
7119 asm, ".8h", ".8b", ".8b",
7124 asm#"2", ".8h", ".16b", ".16b",
7131 asm, ".4s", ".4h", ".4h",
7136 asm#"2", ".4s", ".8h", ".8h",
7143 asm, ".2d", ".2s", ".2s",
7148 asm#"2", ".2d", ".4s", ".4s",
7155 multiclass SIMDLongThreeVectorSQDMLXTiedHS<bit U, bits<4> opc, string asm,
7159 asm, ".4s", ".4h", ".4h",
7166 asm#"2", ".4s", ".8h", ".8h",
7173 asm, ".2d", ".2s", ".2s",
7180 asm#"2", ".2d", ".4s", ".4s",
7187 multiclass SIMDWideThreeVectorBHS<bit U, bits<4> opc, string asm,
7191 asm, ".8h", ".8h", ".8b",
7195 asm#"2", ".8h", ".8h", ".16b",
7200 asm, ".4s", ".4s", ".4h",
7204 asm#"2", ".4s", ".4s", ".8h",
7209 asm, ".2d", ".2d", ".2s",
7213 asm#"2", ".2d", ".2d", ".4s",
7223 string asm, string kind>
7224 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
7246 multiclass SIMDBitwiseExtract<string asm> {
7247 def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> {
7250 def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
7258 string asm, string kind, SDNode OpNode, ValueType valty>
7259 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
7280 multiclass SIMDZipVector<bits<3>opc, string asm,
7283 asm, ".8b", OpNode, v8i8>;
7285 asm, ".16b", OpNode, v16i8>;
7287 asm, ".4h", OpNode, v4i16>;
7289 asm, ".8h", OpNode, v8i16>;
7291 asm, ".2s", OpNode, v2i32>;
7293 asm, ".4s", OpNode, v4i32>;
7295 asm, ".2d", OpNode, v2i64>;
7319 RegisterClass regtype, string asm,
7321 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
7340 dag oops, dag iops, string asm,
7342 : I<oops, iops, asm, "\t$Rd, $Rn, $Rm", "$Rd = $dst", pattern>,
7359 multiclass SIMDThreeScalarD<bit U, bits<5> opc, string asm,
7361 def v1i64 : BaseSIMDThreeScalar<U, 0b111, opc, FPR64, asm,
7365 multiclass SIMDThreeScalarBHSD<bit U, bits<5> opc, string asm,
7367 def v1i64 : BaseSIMDThreeScalar<U, 0b111, opc, FPR64, asm,
7369 def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm, []>;
7370 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
7371 def v1i8 : BaseSIMDThreeScalar<U, 0b001, opc, FPR8 , asm, []>;
7379 multiclass SIMDThreeScalarHS<bit U, bits<5> opc, string asm,
7381 def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm,
7383 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
7386 multiclass SIMDThreeScalarHSTied<bit U, bit R, bits<5> opc, string asm> {
7389 asm, []>;
7392 asm, []>;
7395 multiclass SIMDFPThreeScalar<bit U, bit S, bits<3> opc, string asm,
7400 def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
7402 def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
7406 def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
7415 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<3> opc, string asm,
7418 def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
7420 def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
7423 def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
7433 dag oops, dag iops, string asm, string cstr, list<dag> pat>
7434 : I<oops, iops, asm,
7453 multiclass SIMDThreeScalarMixedHS<bit U, bits<5> opc, string asm,
7457 (ins FPR16:$Rn, FPR16:$Rm), asm, "", []>;
7460 (ins FPR32:$Rn, FPR32:$Rm), asm, "",
7465 multiclass SIMDThreeScalarMixedTiedHS<bit U, bits<5> opc, string asm,
7470 asm, "$Rd = $dst", []>;
7474 asm, "$Rd = $dst",
7486 string asm, list<dag> pat>
7487 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
7508 string asm, list<dag> pat>
7509 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
7528 RegisterClass regtype, string asm, string zero>
7529 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
7548 class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
7549 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
7561 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
7563 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, 0b00, opc, FPR64, asm, "0">;
7569 multiclass SIMDFPCmpTwoScalar<bit U, bit S, bits<5> opc, string asm,
7572 def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, 0b00, opc, FPR64, asm, "0.0">;
7573 def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, 0b00, opc, FPR32, asm, "0.0">;
7575 def v1i16rz : BaseSIMDCmpTwoScalar<U, {S,1}, 0b11, opc, FPR16, asm, "0.0">;
7579 def : InstAlias<asm # "\t$Rd, $Rn, #0",
7581 def : InstAlias<asm # "\t$Rd, $Rn, #0",
7584 def : InstAlias<asm # "\t$Rd, $Rn, #0",
7592 multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
7595 def v1i64 : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
7605 multiclass SIMDFPTwoScalar<bit U, bit S, bits<5> opc, string asm> {
7607 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, 0b00, opc, FPR64, FPR64, asm,[]>;
7608 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,[]>;
7611 def v1f16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,[]>;
7616 multiclass SIMDFPTwoScalarCVT<bit U, bit S, bits<5> opc, string asm,
7619 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, 0b00, opc, FPR64, FPR64, asm,
7621 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,
7625 def v1i16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,
7630 multiclass SIMDTwoScalarBHSD<bit U, bits<5> opc, string asm,
7633 def v1i64 : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
7635 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR32, asm,
7637 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR16, asm, []>;
7638 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR8 , asm, []>;
7645 multiclass SIMDTwoScalarBHSDTied<bit U, bits<5> opc, string asm,
7648 def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
7650 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
7652 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
7653 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
7663 multiclass SIMDTwoScalarMixedBHS<bit U, bits<5> opc, string asm,
7665 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR64, asm,
7667 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR32, asm, []>;
7668 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR16, asm, []>;
7678 string asm, string kind>
7679 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
7695 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
7697 asm, ".2d">;
7701 multiclass SIMDFPPairwiseScalar<bit S, bits<5> opc, string asm> {
7704 asm, ".2h">;
7707 asm, ".2s">;
7709 asm, ".2d">;
7719 string asm, string kind, list<dag> pattern>
7720 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
7738 string asm> {
7740 asm, ".8b", []>;
7742 asm, ".16b", []>;
7744 asm, ".4h", []>;
7746 asm, ".8h", []>;
7748 asm, ".4s", []>;
7751 multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
7753 asm, ".8b", []>;
7755 asm, ".16b", []>;
7757 asm, ".4h", []>;
7759 asm, ".8h", []>;
7761 asm, ".4s", []>;
7765 multiclass SIMDFPAcrossLanes<bits<5> opcode, bit sz1, string asm,
7769 asm, ".4h",
7772 asm, ".8h",
7776 asm, ".4s",
7786 class BaseSIMDInsDup<bit Q, bit op, dag outs, dag ins, string asm,
7788 : I<outs, ins, asm, operands, constraints, pattern>,
7860 Operand idxtype, string asm, list<dag> pattern>
7861 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
7875 class SIMDMovAlias<string asm, string size, Instruction inst,
7877 : InstAlias<asm#"{\t$dst, $src"#size#"$idx" #
8098 RegisterOperand listtype, string asm, string kind>
8099 : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm,
8119 RegisterOperand listtype, string asm, string kind>
8120 : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm,
8138 class SIMDTableLookupAlias<string asm, Instruction inst,
8140 : InstAlias<!strconcat(asm, "\t$dst, $lst, $index"),
8143 multiclass SIMDTableLookup<bit op, string asm> {
8145 asm, ".8b">;
8147 asm, ".8b">;
8149 asm, ".8b">;
8151 asm, ".8b">;
8153 asm, ".16b">;
8155 asm, ".16b">;
8157 asm, ".16b">;
8159 asm, ".16b">;
8161 def : SIMDTableLookupAlias<asm # ".8b",
8164 def : SIMDTableLookupAlias<asm # ".8b",
8167 def : SIMDTableLookupAlias<asm # ".8b",
8170 def : SIMDTableLookupAlias<asm # ".8b",
8173 def : SIMDTableLookupAlias<asm # ".16b",
8176 def : SIMDTableLookupAlias<asm # ".16b",
8179 def : SIMDTableLookupAlias<asm # ".16b",
8182 def : SIMDTableLookupAlias<asm # ".16b",
8187 multiclass SIMDTableLookupTied<bit op, string asm> {
8189 asm, ".8b">;
8191 asm, ".8b">;
8193 asm, ".8b">;
8195 asm, ".8b">;
8197 asm, ".16b">;
8199 asm, ".16b">;
8201 asm, ".16b">;
8203 asm, ".16b">;
8205 def : SIMDTableLookupAlias<asm # ".8b",
8208 def : SIMDTableLookupAlias<asm # ".8b",
8211 def : SIMDTableLookupAlias<asm # ".8b",
8214 def : SIMDTableLookupAlias<asm # ".8b",
8217 def : SIMDTableLookupAlias<asm # ".16b",
8220 def : SIMDTableLookupAlias<asm # ".16b",
8223 def : SIMDTableLookupAlias<asm # ".16b",
8226 def : SIMDTableLookupAlias<asm # ".16b",
8237 string asm, string kind>
8240 asm, "\t$Rd" # kind # ", $Rn, $Rm$idx", "", []>,
8258 multiclass BaseSIMDTableLookupIndexed2<string asm> {
8259 …: BaseSIMDTableLookupIndexed<0b1, {0b10,?,?,0b1}, V128, VecListOne16b, VectorIndexS, asm, ".16b"> {
8263 …def v8f16 : BaseSIMDTableLookupIndexed<0b1, {0b11,?,?,?}, V128, VecListOne8h, VectorIndexH, asm, "…
8269 multiclass BaseSIMDTableLookupIndexed4<string asm> {
8270 …def v16f8 : BaseSIMDTableLookupIndexed<0b1, {0b01,?,0b10}, V128, VecListOne16b, VectorIndexD, asm,…
8274 …def v8f16 : BaseSIMDTableLookupIndexed<0b1, {0b01,?,?,0b1}, V128, VecListTwo8h, VectorIndexS, asm,…
8285 string asm, string kind, Operand idxtype>
8286 : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), asm,
8298 class SIMDScalarDUPAlias<string asm, string size, Instruction inst,
8300 : InstAlias<asm # "{\t$dst, $src" # size # "$index"
8305 multiclass SIMDScalarDUP<string asm> {
8306 def i8 : BaseSIMDScalarDUP<FPR8, V128, asm, ".b", VectorIndexB> {
8311 def i16 : BaseSIMDScalarDUP<FPR16, V128, asm, ".h", VectorIndexH> {
8316 def i32 : BaseSIMDScalarDUP<FPR32, V128, asm, ".s", VectorIndexS> {
8321 def i64 : BaseSIMDScalarDUP<FPR64, V128, asm, ".d", VectorIndexD> {
8351 string asm, string op_string,
8353 : I<oops, iops, asm, op_string, cstr, pattern>,
8370 string opt_shift, string asm, string kind,
8373 !con((ins immtype:$imm8), opt_shift_iop), asm,
8382 string opt_shift, string asm, string kind,
8386 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
8393 RegisterOperand vectype, string asm,
8397 "$shift", asm, kind, pattern> {
8405 RegisterOperand vectype, string asm,
8409 "$shift", asm, kind, pattern> {
8418 RegisterOperand vectype, string asm,
8422 "$shift", asm, kind, pattern> {
8431 RegisterOperand vectype, string asm,
8435 "$shift", asm, kind, pattern> {
8444 string asm> {
8446 asm, ".4h", []>;
8448 asm, ".8h", []>;
8451 asm, ".2s", []>;
8453 asm, ".4s", []>;
8457 bits<2> w_cmode, string asm,
8460 asm, ".4h",
8465 asm, ".8h",
8471 asm, ".2s",
8476 asm, ".4s",
8483 RegisterOperand vectype, string asm,
8487 "$shift", asm, kind, pattern> {
8495 Operand imm_type, string asm,
8498 asm, kind, pattern> {
8502 class SIMDModifiedImmScalarNoShift<bit Q, bit op, bits<4> cmode, string asm,
8504 : BaseSIMDModifiedImm<Q, op, 0, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
8517 RegisterOperand rhs_reg, Operand vec_idx, string asm,
8521 asm,
8547 RegisterOperand rhs_reg, Operand vec_idx, string asm,
8551 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
8580 class BaseSIMDThreeSameVectorBFDot<bit Q, bit U, string asm, string kind1,
8583 …: BaseSIMDThreeSameVectorTied<Q, U, 0b010, 0b11111, RegType, asm, kind1, [(set (AccumType RegType:…
8587 let AsmString = !strconcat(asm,
8592 multiclass SIMDThreeSameVectorBFDot<bit U, string asm> {
8593 def v4bf16 : BaseSIMDThreeSameVectorBFDot<0, U, asm, ".2s", ".4h", V64,
8595 def v8bf16 : BaseSIMDThreeSameVectorBFDot<1, U, asm, ".4s", ".8h", V128,
8599 class BaseSIMDThreeSameVectorBF16DotI<bit Q, bit U, string asm,
8607 asm, "", dst_kind, lhs_kind, rhs_kind,
8621 multiclass SIMDThreeSameVectorBF16DotI<bit U, string asm> {
8623 def v4bf16 : BaseSIMDThreeSameVectorBF16DotI<0, U, asm, ".2s", ".4h",
8625 def v8bf16 : BaseSIMDThreeSameVectorBF16DotI<1, U, asm, ".4s", ".8h",
8630 class SIMDBF16MLAL<bit Q, string asm, SDPatternOperator OpNode>
8631 : BaseSIMDThreeSameVectorTied<Q, 0b1, 0b110, 0b11111, V128, asm, ".4s",
8635 let AsmString = !strconcat(asm, "{\t$Rd.4s, $Rn.8h, $Rm.8h}");
8639 class SIMDBF16MLALIndex<bit Q, string asm, SDPatternOperator OpNode>
8641 (ins V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx), asm,
8667 class SIMDThreeSameVectorBF16MatrixMul<string asm>
8669 V128, asm, ".4s",
8674 let AsmString = !strconcat(asm, "{\t$Rd", ".4s", ", $Rn", ".8h",
8693 class BF16ToSinglePrecision<string asm>
8694 : I<(outs FPR16:$Rd), (ins FPR32:$Rn), asm, "\t$Rd, $Rn", "",
8707 string asm, string dst_kind,
8712 asm, "", dst_kind, ".16b", ".b", []> {
8720 multiclass SIMDThreeSameVectorMLAIndex<bit Q, string asm> {
8721 def v8f16 : BaseSIMDThreeSameVectorIndexB<Q, 0b0, 0b11, 0b0000, asm, ".8h",
8725 multiclass SIMDThreeSameVectorMLALIndex<bit Q, bits<2> sz, string asm> {
8726 def v4f32 : BaseSIMDThreeSameVectorIndexB<Q, 0b1, sz, 0b1000, asm, ".4s",
8734 class SIMDThreeSameVectorMatMul<bit B, bit U, string asm, SDPatternOperator OpNode>
8735 : BaseSIMDThreeSameVectorTied<1, U, 0b100, {0b1010, B}, V128, asm, ".4s",
8739 let AsmString = asm # "{\t$Rd.4s, $Rn.16b, $Rm.16b}";
8744 class BaseSIMDThreeSameVectorIndexS<bit Q, bit U, bits<2> size, bits<4> opc, string asm,
8750 VectorIndexS, asm, "", dst_kind, lhs_kind, rhs_kind,
8762 multiclass SIMDThreeSameVectorDotIndex<bit U, bit Mixed, bits<2> size, string asm,
8764 def v8i8 : BaseSIMDThreeSameVectorIndexS<0, U, size, {0b111, Mixed}, asm, ".2s", ".8b", ".4b",
8766 def v16i8 : BaseSIMDThreeSameVectorIndexS<1, U, size, {0b111, Mixed}, asm, ".4s", ".16b", ".4b",
8771 multiclass SIMDThreeSameVectorFP8DOT4Index<string asm> {
8772 def v8f8 : BaseSIMDThreeSameVectorIndexS<0b0, 0b0, 0b00, 0b0000, asm, ".2s", ".8b", ".4b",
8774 def v16f8 : BaseSIMDThreeSameVectorIndexS<0b1, 0b0, 0b00, 0b0000, asm, ".4s", ".16b",".4b",
8780 class BaseSIMDThreeSameVectorIndexH<bit Q, bit U, bits<2> sz, bits<4> opc, string asm,
8786 VectorIndexH, asm, "", dst_kind, lhs_kind, rhs_kind,
8799 multiclass SIMDThreeSameVectorFMLIndex<bit U, bits<4> opc, string asm,
8801 def v4f16 : BaseSIMDThreeSameVectorIndexH<0, U, 0b10, opc, asm, ".2s", ".2h", ".h",
8803 def v8f16 : BaseSIMDThreeSameVectorIndexH<1, U, 0b10, opc, asm, ".4s", ".4h", ".h",
8810 multiclass SIMDThreeSameVectorFP8DOT2Index<string asm> {
8811 def v4f16 : BaseSIMDThreeSameVectorIndexH<0b0, 0b0, 0b01, 0b0000, asm, ".4h", ".8b", ".2b",
8813 def v8f16 : BaseSIMDThreeSameVectorIndexH<0b1, 0b0, 0b01, 0b0000, asm, ".8h", ".16b", ".2b",
8817 multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
8824 asm, ".4h", ".4h", ".4h", ".h",
8837 asm, ".8h", ".8h", ".8h", ".h",
8851 asm, ".2s", ".2s", ".2s", ".s",
8863 asm, ".4s", ".4s", ".4s", ".s",
8875 asm, ".2d", ".2d", ".2d", ".d",
8887 asm, ".h", "", "", ".h",
8901 asm, ".s", "", "", ".s",
8913 asm, ".d", "", "", ".d",
9024 multiclass SIMDFPIndexedTied<bit U, bits<4> opc, string asm> {
9028 asm, ".4h", ".4h", ".4h", ".h", []> {
9038 asm, ".8h", ".8h", ".8h", ".h", []> {
9048 asm, ".2s", ".2s", ".2s", ".s", []> {
9057 asm, ".4s", ".4s", ".4s", ".s", []> {
9066 asm, ".2d", ".2d", ".2d", ".d", []> {
9075 asm, ".h", "", "", ".h", []> {
9085 asm, ".s", "", "", ".s", []> {
9093 asm, ".d", "", "", ".d", []> {
9158 multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
9162 asm, ".4h", ".4h", ".4h", ".h",
9175 asm, ".8h", ".8h", ".8h", ".h",
9188 asm, ".2s", ".2s", ".2s", ".s",
9200 asm, ".4s", ".4s", ".4s", ".s",
9211 asm, ".h", "", "", ".h", []> {
9220 asm, ".s", "", "", ".s",
9231 multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
9236 asm, ".4h", ".4h", ".4h", ".h",
9249 asm, ".8h", ".8h", ".8h", ".h",
9262 asm, ".2s", ".2s", ".2s", ".s",
9274 asm, ".4s", ".4s", ".4s", ".s",
9284 multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
9288 asm, ".4h", ".4h", ".4h", ".h",
9301 asm, ".8h", ".8h", ".8h", ".h",
9314 asm, ".2s", ".2s", ".2s", ".s",
9326 asm, ".4s", ".4s", ".4s", ".s",
9336 multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
9341 asm, ".4s", ".4s", ".4h", ".h",
9354 asm#"2", ".4s", ".4s", ".8h", ".h",
9368 asm, ".2d", ".2d", ".2s", ".s",
9380 asm#"2", ".2d", ".2d", ".4s", ".s",
9391 asm, ".h", "", "", ".h", []> {
9400 asm, ".s", "", "", ".s", []> {
9407 multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
9412 asm, ".4s", ".4s", ".4h", ".h",
9428 asm#"2", ".4s", ".4s", ".8h", ".h",
9443 asm, ".2d", ".2d", ".2s", ".s",
9457 asm#"2", ".2d", ".2d", ".4s", ".s",
9470 asm, ".h", "", "", ".h", []> {
9504 asm, ".s", "", "", ".s",
9518 multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
9524 asm, ".4s", ".4s", ".4h", ".h",
9537 asm#"2", ".4s", ".4s", ".8h", ".h",
9551 asm, ".2d", ".2d", ".2s", ".s",
9563 asm#"2", ".2d", ".2d", ".4s", ".s",
9574 multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
9580 asm, ".4s", ".4s", ".4h", ".h",
9593 asm#"2", ".4s", ".4s", ".8h", ".h",
9607 asm, ".2d", ".2d", ".2s", ".s",
9619 asm#"2", ".2d", ".2d", ".4s", ".s",
9638 Operand immtype, string asm, list<dag> pattern>
9640 asm, "\t$Rd, $Rn, $imm", "", pattern>,
9658 Operand immtype, string asm, list<dag> pattern>
9660 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
9676 multiclass SIMDFPScalarRShift<bit U, bits<5> opc, string asm> {
9679 FPR16, FPR16, vecshiftR16, asm, []> {
9684 FPR32, FPR32, vecshiftR32, asm, []> {
9688 FPR64, FPR64, vecshiftR64, asm, []> {
9693 multiclass SIMDScalarRShiftD<bit U, bits<5> opc, string asm,
9696 FPR64, FPR64, vecshiftR64, asm,
9706 multiclass SIMDScalarRShiftDTied<bit U, bits<5> opc, string asm,
9709 FPR64, FPR64, vecshiftR64, asm,
9721 multiclass SIMDScalarLShiftD<bit U, bits<5> opc, string asm,
9724 FPR64, FPR64, vecshiftL64, asm,
9735 multiclass SIMDScalarLShiftDTied<bit U, bits<5> opc, string asm> {
9737 FPR64, FPR64, vecshiftL64, asm, []> {
9743 multiclass SIMDScalarRShiftBHS<bit U, bits<5> opc, string asm,
9746 FPR8, FPR16, vecshiftR8, asm, []> {
9751 FPR16, FPR32, vecshiftR16, asm, []> {
9756 FPR32, FPR64, vecshiftR32, asm,
9762 multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm,
9765 FPR8, FPR8, vecshiftL8, asm, []> {
9770 FPR16, FPR16, vecshiftL16, asm, []> {
9775 FPR32, FPR32, vecshiftL32, asm,
9781 FPR64, FPR64, vecshiftL64, asm,
9790 multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {
9792 FPR8, FPR8, vecshiftR8, asm, []> {
9797 FPR16, FPR16, vecshiftR16, asm, []> {
9802 FPR32, FPR32, vecshiftR32, asm, []> {
9807 FPR64, FPR64, vecshiftR64, asm, []> {
9820 string asm, string dst_kind, string src_kind,
9823 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
9843 string asm, string dst_kind, string src_kind,
9846 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
9862 multiclass SIMDVectorRShiftSD<bit U, bits<5> opc, string asm,
9867 asm, ".4h", ".4h",
9875 asm, ".8h", ".8h",
9883 asm, ".2s", ".2s",
9891 asm, ".4s", ".4s",
9899 asm, ".2d", ".2d",
9906 multiclass SIMDVectorRShiftToFP<bit U, bits<5> opc, string asm,
9911 asm, ".4h", ".4h",
9919 asm, ".8h", ".8h",
9928 asm, ".2s", ".2s",
9936 asm, ".4s", ".4s",
9944 asm, ".2d", ".2d",
9951 multiclass SIMDVectorRShiftNarrowBHS<bit U, bits<5> opc, string asm,
9955 asm, ".8b", ".8h",
9963 asm#"2", ".16b", ".8h", []> {
9971 asm, ".4h", ".4s",
9979 asm#"2", ".8h", ".4s", []> {
9987 asm, ".2s", ".2d",
9995 asm#"2", ".4s", ".2d", []> {
10023 multiclass SIMDVectorLShiftBHSD<bit U, bits<5> opc, string asm,
10027 asm, ".8b", ".8b",
10036 asm, ".16b", ".16b",
10045 asm, ".4h", ".4h",
10054 asm, ".8h", ".8h",
10063 asm, ".2s", ".2s",
10072 asm, ".4s", ".4s",
10081 asm, ".2d", ".2d",
10089 multiclass SIMDVectorRShiftBHSD<bit U, bits<5> opc, string asm,
10093 asm, ".8b", ".8b",
10102 asm, ".16b", ".16b",
10111 asm, ".4h", ".4h",
10120 asm, ".8h", ".8h",
10129 asm, ".2s", ".2s",
10138 asm, ".4s", ".4s",
10147 asm, ".2d", ".2d",
10156 multiclass SIMDVectorRShiftBHSDTied<bit U, bits<5> opc, string asm,
10159 V64, V64, vecshiftR8, asm, ".8b", ".8b",
10168 V128, V128, vecshiftR8, asm, ".16b", ".16b",
10177 V64, V64, vecshiftR16, asm, ".4h", ".4h",
10186 V128, V128, vecshiftR16, asm, ".8h", ".8h",
10195 V64, V64, vecshiftR32, asm, ".2s", ".2s",
10204 V128, V128, vecshiftR32, asm, ".4s", ".4s",
10214 asm, ".2d", ".2d", [(set (v2i64 V128:$dst),
10222 multiclass SIMDVectorLShiftBHSDTied<bit U, bits<5> opc, string asm,
10226 asm, ".8b", ".8b",
10236 asm, ".16b", ".16b",
10246 asm, ".4h", ".4h",
10256 asm, ".8h", ".8h",
10266 asm, ".2s", ".2s",
10276 asm, ".4s", ".4s",
10286 asm, ".2d", ".2d",
10295 multiclass SIMDVectorLShiftLongBHSD<bit U, bits<5> opc, string asm,
10298 V128, V64, vecshiftL8, asm, ".8h", ".8b",
10306 asm#"2", ".8h", ".16b",
10314 V128, V64, vecshiftL16, asm, ".4s", ".4h",
10322 asm#"2", ".4s", ".8h",
10331 V128, V64, vecshiftL32, asm, ".2d", ".2s",
10339 asm#"2", ".2d", ".4s",
10357 string asm, dag oops, dag iops, list<dag> pattern>
10358 : I<oops, iops, asm, "\t$Vt, [$Rn]", "", pattern> {
10373 string asm, dag oops, dag iops>
10374 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
10392 multiclass SIMDLdStAliases<string BaseName, string asm, string layout, string Count,
10398 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
10408 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
10418 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
10427 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
10434 multiclass BaseSIMDLdN<string BaseName, string Count, string asm, string veclist,
10437 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
10440 def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm,
10443 def v4s : BaseSIMDLdSt<1, 1, opcode, 0b10, asm,
10446 def v2d : BaseSIMDLdSt<1, 1, opcode, 0b11, asm,
10449 def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm,
10452 def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm,
10455 def v2s : BaseSIMDLdSt<0, 1, opcode, 0b10, asm,
10460 def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
10465 def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
10470 def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm,
10475 def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm,
10480 def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
10485 def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
10490 def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm,
10497 defm : SIMDLdStAliases<BaseName, asm, "16b", Count, Offset128, 128>;
10498 defm : SIMDLdStAliases<BaseName, asm, "8h", Count, Offset128, 128>;
10499 defm : SIMDLdStAliases<BaseName, asm, "4s", Count, Offset128, 128>;
10500 defm : SIMDLdStAliases<BaseName, asm, "2d", Count, Offset128, 128>;
10501 defm : SIMDLdStAliases<BaseName, asm, "8b", Count, Offset64, 64>;
10502 defm : SIMDLdStAliases<BaseName, asm, "4h", Count, Offset64, 64>;
10503 defm : SIMDLdStAliases<BaseName, asm, "2s", Count, Offset64, 64>;
10507 multiclass BaseSIMDStN<string BaseName, string Count, string asm, string veclist,
10510 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
10513 def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs),
10516 def v4s : BaseSIMDLdSt<1, 0, opcode, 0b10, asm, (outs),
10519 def v2d : BaseSIMDLdSt<1, 0, opcode, 0b11, asm, (outs),
10522 def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs),
10525 def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs),
10528 def v2s : BaseSIMDLdSt<0, 0, opcode, 0b10, asm, (outs),
10532 def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm,
10537 def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm,
10542 def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm,
10547 def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm,
10552 def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm,
10557 def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm,
10562 def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm,
10569 defm : SIMDLdStAliases<BaseName, asm, "16b", Count, Offset128, 128>;
10570 defm : SIMDLdStAliases<BaseName, asm, "8h", Count, Offset128, 128>;
10571 defm : SIMDLdStAliases<BaseName, asm, "4s", Count, Offset128, 128>;
10572 defm : SIMDLdStAliases<BaseName, asm, "2d", Count, Offset128, 128>;
10573 defm : SIMDLdStAliases<BaseName, asm, "8b", Count, Offset64, 64>;
10574 defm : SIMDLdStAliases<BaseName, asm, "4h", Count, Offset64, 64>;
10575 defm : SIMDLdStAliases<BaseName, asm, "2s", Count, Offset64, 64>;
10578 multiclass BaseSIMDLd1<string BaseName, string Count, string asm, string veclist,
10580 : BaseSIMDLdN<BaseName, Count, asm, veclist, Offset128, Offset64, opcode> {
10584 def v1d : BaseSIMDLdSt<0, 1, opcode, 0b11, asm,
10588 def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm,
10595 defm : SIMDLdStAliases<BaseName, asm, "1d", Count, Offset64, 64>;
10598 multiclass BaseSIMDSt1<string BaseName, string Count, string asm, string veclist,
10600 : BaseSIMDStN<BaseName, Count, asm, veclist, Offset128, Offset64, opcode> {
10604 def v1d : BaseSIMDLdSt<0, 0, opcode, 0b11, asm, (outs),
10608 def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm,
10615 defm : SIMDLdStAliases<BaseName, asm, "1d", Count, Offset64, 64>;
10618 multiclass SIMDLd1Multiple<string asm> {
10619 defm One : BaseSIMDLd1<NAME, "One", asm, "VecListOne", 16, 8, 0b0111>;
10620 defm Two : BaseSIMDLd1<NAME, "Two", asm, "VecListTwo", 32, 16, 0b1010>;
10621 defm Three : BaseSIMDLd1<NAME, "Three", asm, "VecListThree", 48, 24, 0b0110>;
10622 defm Four : BaseSIMDLd1<NAME, "Four", asm, "VecListFour", 64, 32, 0b0010>;
10625 multiclass SIMDSt1Multiple<string asm> {
10626 defm One : BaseSIMDSt1<NAME, "One", asm, "VecListOne", 16, 8, 0b0111>;
10627 defm Two : BaseSIMDSt1<NAME, "Two", asm, "VecListTwo", 32, 16, 0b1010>;
10628 defm Three : BaseSIMDSt1<NAME, "Three", asm, "VecListThree", 48, 24, 0b0110>;
10629 defm Four : BaseSIMDSt1<NAME, "Four", asm, "VecListFour", 64, 32, 0b0010>;
10632 multiclass SIMDLd2Multiple<string asm> {
10633 defm Two : BaseSIMDLdN<NAME, "Two", asm, "VecListTwo", 32, 16, 0b1000>;
10636 multiclass SIMDSt2Multiple<string asm> {
10637 defm Two : BaseSIMDStN<NAME, "Two", asm, "VecListTwo", 32, 16, 0b1000>;
10640 multiclass SIMDLd3Multiple<string asm> {
10641 defm Three : BaseSIMDLdN<NAME, "Three", asm, "VecListThree", 48, 24, 0b0100>;
10644 multiclass SIMDSt3Multiple<string asm> {
10645 defm Three : BaseSIMDStN<NAME, "Three", asm, "VecListThree", 48, 24, 0b0100>;
10648 multiclass SIMDLd4Multiple<string asm> {
10649 defm Four : BaseSIMDLdN<NAME, "Four", asm, "VecListFour", 64, 32, 0b0000>;
10652 multiclass SIMDSt4Multiple<string asm> {
10653 defm Four : BaseSIMDStN<NAME, "Four", asm, "VecListFour", 64, 32, 0b0000>;
10661 string asm, string operands, string cst,
10663 : I<oops, iops, asm, operands, cst, pattern> {
10676 string asm, string operands, string cst,
10678 : I<oops, iops, asm, operands, "$Vt = $dst," # cst, pattern> {
10692 class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
10694 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn]", "",
10705 string asm, DAGOperand listtype, DAGOperand GPR64pi>
10706 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm",
10718 multiclass SIMDLdrAliases<string BaseName, string asm, string layout, string Count,
10724 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
10734 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
10744 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
10753 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
10760 multiclass SIMDLdR<bit R, bits<3> opcode, bit S, string asm, string Count,
10762 def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
10764 def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
10766 def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
10768 def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
10770 def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm,
10772 def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm,
10774 def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm,
10776 def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm,
10779 def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
10782 def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
10785 def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
10788 def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
10791 def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm,
10794 def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm,
10797 def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm,
10800 def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm,
10804 defm : SIMDLdrAliases<NAME, asm, "8b", Count, Offset1, 64>;
10805 defm : SIMDLdrAliases<NAME, asm, "16b", Count, Offset1, 128>;
10806 defm : SIMDLdrAliases<NAME, asm, "4h", Count, Offset2, 64>;
10807 defm : SIMDLdrAliases<NAME, asm, "8h", Count, Offset2, 128>;
10808 defm : SIMDLdrAliases<NAME, asm, "2s", Count, Offset4, 64>;
10809 defm : SIMDLdrAliases<NAME, asm, "4s", Count, Offset4, 128>;
10810 defm : SIMDLdrAliases<NAME, asm, "1d", Count, Offset8, 64>;
10811 defm : SIMDLdrAliases<NAME, asm, "2d", Count, Offset8, 128>;
10814 class SIMDLdStSingleB<bit L, bit R, bits<3> opcode, string asm,
10816 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
10826 class SIMDLdStSingleBTied<bit L, bit R, bits<3> opcode, string asm,
10828 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
10838 class SIMDLdStSingleBPost<bit L, bit R, bits<3> opcode, string asm,
10840 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
10851 class SIMDLdStSingleBTiedPost<bit L, bit R, bits<3> opcode, string asm,
10853 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
10865 class SIMDLdStSingleH<bit L, bit R, bits<3> opcode, bit size, string asm,
10867 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
10878 class SIMDLdStSingleHTied<bit L, bit R, bits<3> opcode, bit size, string asm,
10880 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
10892 class SIMDLdStSingleHPost<bit L, bit R, bits<3> opcode, bit size, string asm,
10894 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
10906 class SIMDLdStSingleHTiedPost<bit L, bit R, bits<3> opcode, bit size, string asm,
10908 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
10920 class SIMDLdStSingleS<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
10922 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
10932 class SIMDLdStSingleSTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
10934 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
10945 string asm, dag oops, dag iops>
10946 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
10958 string asm, dag oops, dag iops>
10959 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
10970 class SIMDLdStSingleD<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
10972 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
10982 class SIMDLdStSingleDTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
10984 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
10995 string asm, dag oops, dag iops>
10996 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
11008 string asm, dag oops, dag iops>
11009 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
11022 multiclass SIMDLdSingleBTied<bit R, bits<3> opcode, string asm,
11025 def i8 : SIMDLdStSingleBTied<1, R, opcode, asm,
11030 def i8_POST : SIMDLdStSingleBTiedPost<1, R, opcode, asm,
11036 multiclass SIMDLdSingleHTied<bit R, bits<3> opcode, bit size, string asm,
11039 def i16 : SIMDLdStSingleHTied<1, R, opcode, size, asm,
11044 def i16_POST : SIMDLdStSingleHTiedPost<1, R, opcode, size, asm,
11050 multiclass SIMDLdSingleSTied<bit R, bits<3> opcode, bits<2> size,string asm,
11053 def i32 : SIMDLdStSingleSTied<1, R, opcode, size, asm,
11058 def i32_POST : SIMDLdStSingleSTiedPost<1, R, opcode, size, asm,
11064 multiclass SIMDLdSingleDTied<bit R, bits<3> opcode, bits<2> size, string asm,
11066 def i64 : SIMDLdStSingleDTied<1, R, opcode, size, asm,
11071 def i64_POST : SIMDLdStSingleDTiedPost<1, R, opcode, size, asm,
11077 multiclass SIMDStSingleB<bit R, bits<3> opcode, string asm,
11079 def i8 : SIMDLdStSingleB<0, R, opcode, asm,
11083 def i8_POST : SIMDLdStSingleBPost<0, R, opcode, asm,
11089 multiclass SIMDStSingleH<bit R, bits<3> opcode, bit size, string asm,
11091 def i16 : SIMDLdStSingleH<0, R, opcode, size, asm,
11095 def i16_POST : SIMDLdStSingleHPost<0, R, opcode, size, asm,
11101 multiclass SIMDStSingleS<bit R, bits<3> opcode, bits<2> size,string asm,
11103 def i32 : SIMDLdStSingleS<0, R, opcode, size, asm,
11107 def i32_POST : SIMDLdStSingleSPost<0, R, opcode, size, asm,
11113 multiclass SIMDStSingleD<bit R, bits<3> opcode, bits<2> size, string asm,
11115 def i64 : SIMDLdStSingleD<0, R, opcode, size, asm,
11119 def i64_POST : SIMDLdStSingleDPost<0, R, opcode, size, asm,
11125 multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
11131 def : InstAlias<asm # "\t$Vt$idx, [$Rn], #" # Offset,
11141 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], #" # Offset,
11151 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn]",
11160 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], $Xm",
11168 multiclass SIMDLdSt1SingleAliases<string asm> {
11169 defm "" : SIMDLdStSingleAliases<asm, "b", "i8", "One", 1, VectorIndexB>;
11170 defm "" : SIMDLdStSingleAliases<asm, "h", "i16", "One", 2, VectorIndexH>;
11171 defm "" : SIMDLdStSingleAliases<asm, "s", "i32", "One", 4, VectorIndexS>;
11172 defm "" : SIMDLdStSingleAliases<asm, "d", "i64", "One", 8, VectorIndexD>;
11175 multiclass SIMDLdSt2SingleAliases<string asm> {
11176 defm "" : SIMDLdStSingleAliases<asm, "b", "i8", "Two", 2, VectorIndexB>;
11177 defm "" : SIMDLdStSingleAliases<asm, "h", "i16", "Two", 4, VectorIndexH>;
11178 defm "" : SIMDLdStSingleAliases<asm, "s", "i32", "Two", 8, VectorIndexS>;
11179 defm "" : SIMDLdStSingleAliases<asm, "d", "i64", "Two", 16, VectorIndexD>;
11182 multiclass SIMDLdSt3SingleAliases<string asm> {
11183 defm "" : SIMDLdStSingleAliases<asm, "b", "i8", "Three", 3, VectorIndexB>;
11184 defm "" : SIMDLdStSingleAliases<asm, "h", "i16", "Three", 6, VectorIndexH>;
11185 defm "" : SIMDLdStSingleAliases<asm, "s", "i32", "Three", 12, VectorIndexS>;
11186 defm "" : SIMDLdStSingleAliases<asm, "d", "i64", "Three", 24, VectorIndexD>;
11189 multiclass SIMDLdSt4SingleAliases<string asm> {
11190 defm "" : SIMDLdStSingleAliases<asm, "b", "i8", "Four", 4, VectorIndexB>;
11191 defm "" : SIMDLdStSingleAliases<asm, "h", "i16", "Four", 8, VectorIndexH>;
11192 defm "" : SIMDLdStSingleAliases<asm, "s", "i32", "Four", 16, VectorIndexS>;
11193 defm "" : SIMDLdStSingleAliases<asm, "d", "i64", "Four", 32, VectorIndexD>;
11204 RegisterOperand regtype, string asm,
11206 : BaseSIMDThreeSameVectorTied<Q, U, {size,0}, opcode, regtype, asm, kind,
11209 multiclass SIMDThreeSameVectorSQRDMLxHTiedHS<bit U, bits<5> opc, string asm,
11211 def v4i16 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b01, opc, V64, asm, ".4h",
11214 def v8i16 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b01, opc, V128, asm, ".8h",
11217 def v2i32 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b10, opc, V64, asm, ".2s",
11220 def v4i32 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b10, opc, V128, asm, ".4s",
11225 multiclass SIMDIndexedSQRDMLxHSDTied<bit U, bits<4> opc, string asm,
11229 asm, ".4h", ".4h", ".4h", ".h",
11242 asm, ".8h", ".8h", ".8h", ".h",
11255 asm, ".2s", ".2s", ".2s", ".s",
11266 asm, ".4s", ".4s", ".4s", ".s",
11278 VectorIndexH, asm, ".h", "", "", ".h",
11288 asm, ".s", "", "", ".s",
11327 string asm, string kind, list<dag> pattern>
11328 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, rottype:$rot), asm,
11354 string asm, SDPatternOperator OpNode>{
11357 asm, ".4h",
11364 asm, ".8h",
11373 asm, ".2s",
11380 asm, ".4s",
11387 asm, ".2d",
11399 Operand rottype, string asm,
11402 (ins regtype:$Rd, regtype:$Rn, regtype:$Rm, rottype:$rot), asm,
11425 Operand rottype, string asm,
11429 rottype, asm, ".4h",
11436 rottype, asm, ".8h",
11445 rottype, asm, ".2s",
11452 rottype, asm, ".4s",
11459 rottype, asm, ".2d",
11472 Operand rottype, string asm, string apple_kind,
11477 asm,
11508 string asm> {
11511 V64, V128, VectorIndexD, rottype, asm, ".4h", ".4h",
11519 V128, V128, V128, VectorIndexS, rottype, asm, ".8h",
11529 V128, V128, V128, VectorIndexD, rottype, asm, ".4s",
11543 class AESBase<bits<4> opc, string asm, dag outs, dag ins, string cstr,
11545 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
11556 class AESInst<bits<4> opc, string asm, Intrinsic OpNode>
11557 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
11560 class AESTiedInst<bits<4> opc, string asm, Intrinsic OpNode>
11561 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
11567 class SHA3OpTiedInst<bits<3> opc, string asm, string dst_lhs_kind,
11569 : I<oops, iops, asm,
11585 class SHATiedInstQSV<bits<3> opc, string asm, Intrinsic OpNode>
11586 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
11592 class SHATiedInstVVV<bits<3> opc, string asm, Intrinsic OpNode>
11593 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
11599 class SHATiedInstQQV<bits<3> opc, string asm, Intrinsic OpNode>
11600 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
11607 class SHA2OpInst<bits<4> opc, string asm, string kind,
11610 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
11622 class SHATiedInstVV<bits<4> opc, string asm, Intrinsic OpNode>
11623 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
11628 class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode>
11629 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
11633 class BaseCryptoV82<dag oops, dag iops, string asm, string asmops, string cst,
11635 : I <oops, iops, asm, asmops, cst, pattern>, Sched<[WriteVq]> {
11643 class CryptoRRTied<bits<1>op0, bits<2>op1, string asm, string asmops>
11644 : BaseCryptoV82<(outs V128:$Vdst), (ins V128:$Vd, V128:$Vn), asm, asmops,
11653 class CryptoRRTied_2D<bits<1>op0, bits<2>op1, string asm>
11654 : CryptoRRTied<op0, op1, asm, "{\t$Vd.2d, $Vn.2d|.2d\t$Vd, $Vn}">;
11655 class CryptoRRTied_4S<bits<1>op0, bits<2>op1, string asm>
11656 : CryptoRRTied<op0, op1, asm, "{\t$Vd.4s, $Vn.4s|.4s\t$Vd, $Vn}">;
11658 class CryptoRRR<bits<1> op0, bits<2>op1, dag oops, dag iops, string asm,
11660 : BaseCryptoV82<oops, iops, asm , asmops, cst, []> {
11669 class CryptoRRR_2D<bits<1> op0, bits<2>op1, string asm>
11670 : CryptoRRR<op0, op1, (outs V128:$Vd), (ins V128:$Vn, V128:$Vm), asm,
11672 class CryptoRRRTied_2D<bits<1> op0, bits<2>op1, string asm>
11673 : CryptoRRR<op0, op1, (outs V128:$Vdst), (ins V128:$Vd, V128:$Vn, V128:$Vm), asm,
11675 class CryptoRRR_4S<bits<1> op0, bits<2>op1, string asm>
11676 : CryptoRRR<op0, op1, (outs V128:$Vd), (ins V128:$Vn, V128:$Vm), asm,
11678 class CryptoRRRTied_4S<bits<1> op0, bits<2>op1, string asm>
11679 : CryptoRRR<op0, op1, (outs V128:$Vdst), (ins V128:$Vd, V128:$Vn, V128:$Vm), asm,
11681 class CryptoRRRTied<bits<1> op0, bits<2>op1, string asm>
11683 asm, "{\t$Vd, $Vn, $Vm.2d|.2d\t$Vd, $Vn, $Vm}", "$Vd = $Vdst">;
11685 class CryptoRRRR<bits<2>op0, string asm, string asmops>
11686 : BaseCryptoV82<(outs V128:$Vd), (ins V128:$Vn, V128:$Vm, V128:$Va), asm,
11696 class CryptoRRRR_16B<bits<2>op0, string asm>
11697 : CryptoRRRR<op0, asm, "{\t$Vd.16b, $Vn.16b, $Vm.16b, $Va.16b" #
11700 class CryptoRRRR_4S<bits<2>op0, string asm>
11701 : CryptoRRRR<op0, asm, "{\t$Vd.4s, $Vn.4s, $Vm.4s, $Va.4s" #
11705 class CryptoRRRi6<string asm>
11706 : BaseCryptoV82<(outs V128:$Vd), (ins V128:$Vn, V128:$Vm, uimm6:$imm), asm,
11718 class CryptoRRRi2Tied<bits<1>op0, bits<2>op1, string asm>
11721 asm, "{\t$Vd.4s, $Vn.4s, $Vm.s$imm" #
11763 class BaseCASEncoding<dag oops, dag iops, string asm, string operands,
11765 : I<oops, iops, asm, operands, cstr, pattern> {
11968 class BaseSTOPregister<string asm, RegisterClass OP, Register Reg,
11970 InstAlias<asm # "\t$Rs, [$Rn]", (inst Reg, OP:$Rs, GPR64sp:$Rn)>;
11972 multiclass STOPregister<string asm, string instr> {
11973 def : BaseSTOPregister<asm # "lb", GPR32, WZR,
11975 def : BaseSTOPregister<asm # "lh", GPR32, WZR,
11977 def : BaseSTOPregister<asm # "l", GPR32, WZR,
11979 def : BaseSTOPregister<asm # "l", GPR64, XZR,
11981 def : BaseSTOPregister<asm # "b", GPR32, WZR,
11983 def : BaseSTOPregister<asm # "h", GPR32, WZR,
11985 def : BaseSTOPregister<asm, GPR32, WZR,
11987 def : BaseSTOPregister<asm, GPR64, XZR,
12021 bits<2> op2, string asm>
12024 asm, "\t[$Rd]!, [$Rs]!, $Rn!",
12047 class MOPSMemoryCopy<bits<2> opcode, bits<2> op1, bits<2> op2, string asm>
12048 : MOPSMemoryCopyMoveBase<0, opcode, op1, op2, asm>;
12050 class MOPSMemoryMove<bits<2> opcode, bits<2> op1, bits<2> op2, string asm>
12051 : MOPSMemoryCopyMoveBase<1, opcode, op1, op2, asm>;
12054 string asm>
12057 asm, "\t[$Rd]!, $Rn!, $Rm",
12079 class MOPSMemorySet<bits<2> opcode, bit op1, bit op2, string asm>
12080 : MOPSMemorySetBase<0, opcode, op1, op2, asm>;
12082 class MOPSMemorySetTagging<bits<2> opcode, bit op1, bit op2, string asm>
12083 : MOPSMemorySetBase<1, opcode, op1, op2, asm>;
12085 multiclass MOPSMemoryCopyInsns<bits<2> opcode, string asm> {
12086 def "" : MOPSMemoryCopy<opcode, 0b00, 0b00, asm>;
12087 def WN : MOPSMemoryCopy<opcode, 0b00, 0b01, asm # "wn">;
12088 def RN : MOPSMemoryCopy<opcode, 0b00, 0b10, asm # "rn">;
12089 def N : MOPSMemoryCopy<opcode, 0b00, 0b11, asm # "n">;
12090 def WT : MOPSMemoryCopy<opcode, 0b01, 0b00, asm # "wt">;
12091 def WTWN : MOPSMemoryCopy<opcode, 0b01, 0b01, asm # "wtwn">;
12092 def WTRN : MOPSMemoryCopy<opcode, 0b01, 0b10, asm # "wtrn">;
12093 def WTN : MOPSMemoryCopy<opcode, 0b01, 0b11, asm # "wtn">;
12094 def RT : MOPSMemoryCopy<opcode, 0b10, 0b00, asm # "rt">;
12095 def RTWN : MOPSMemoryCopy<opcode, 0b10, 0b01, asm # "rtwn">;
12096 def RTRN : MOPSMemoryCopy<opcode, 0b10, 0b10, asm # "rtrn">;
12097 def RTN : MOPSMemoryCopy<opcode, 0b10, 0b11, asm # "rtn">;
12098 def T : MOPSMemoryCopy<opcode, 0b11, 0b00, asm # "t">;
12099 def TWN : MOPSMemoryCopy<opcode, 0b11, 0b01, asm # "twn">;
12100 def TRN : MOPSMemoryCopy<opcode, 0b11, 0b10, asm # "trn">;
12101 def TN : MOPSMemoryCopy<opcode, 0b11, 0b11, asm # "tn">;
12104 multiclass MOPSMemoryMoveInsns<bits<2> opcode, string asm> {
12105 def "" : MOPSMemoryMove<opcode, 0b00, 0b00, asm>;
12106 def WN : MOPSMemoryMove<opcode, 0b00, 0b01, asm # "wn">;
12107 def RN : MOPSMemoryMove<opcode, 0b00, 0b10, asm # "rn">;
12108 def N : MOPSMemoryMove<opcode, 0b00, 0b11, asm # "n">;
12109 def WT : MOPSMemoryMove<opcode, 0b01, 0b00, asm # "wt">;
12110 def WTWN : MOPSMemoryMove<opcode, 0b01, 0b01, asm # "wtwn">;
12111 def WTRN : MOPSMemoryMove<opcode, 0b01, 0b10, asm # "wtrn">;
12112 def WTN : MOPSMemoryMove<opcode, 0b01, 0b11, asm # "wtn">;
12113 def RT : MOPSMemoryMove<opcode, 0b10, 0b00, asm # "rt">;
12114 def RTWN : MOPSMemoryMove<opcode, 0b10, 0b01, asm # "rtwn">;
12115 def RTRN : MOPSMemoryMove<opcode, 0b10, 0b10, asm # "rtrn">;
12116 def RTN : MOPSMemoryMove<opcode, 0b10, 0b11, asm # "rtn">;
12117 def T : MOPSMemoryMove<opcode, 0b11, 0b00, asm # "t">;
12118 def TWN : MOPSMemoryMove<opcode, 0b11, 0b01, asm # "twn">;
12119 def TRN : MOPSMemoryMove<opcode, 0b11, 0b10, asm # "trn">;
12120 def TN : MOPSMemoryMove<opcode, 0b11, 0b11, asm # "tn">;
12123 multiclass MOPSMemorySetInsns<bits<2> opcode, string asm> {
12124 def "" : MOPSMemorySet<opcode, 0, 0, asm>;
12125 def T : MOPSMemorySet<opcode, 1, 0, asm # "t">;
12126 def N : MOPSMemorySet<opcode, 0, 1, asm # "n">;
12127 def TN : MOPSMemorySet<opcode, 1, 1, asm # "tn">;
12130 multiclass MOPSMemorySetTaggingInsns<bits<2> opcode, string asm> {
12131 def "" : MOPSMemorySetTagging<opcode, 0, 0, asm>;
12132 def T : MOPSMemorySetTagging<opcode, 1, 0, asm # "t">;
12133 def N : MOPSMemorySetTagging<opcode, 0, 1, asm # "n">;
12134 def TN : MOPSMemorySetTagging<opcode, 1, 1, asm # "tn">;
12146 RegisterClass regtype, ImmLeaf immtype, string asm,
12149 asm, "\t$Rd, $Rn, $imm", "",
12166 RegisterClass regtype, string asm,
12168 : BaseTwoOperandRegReg<size, 0b0, {0,1,1,0,?,?}, regtype, asm, OpNode>,
12178 RegisterClass regtype, ImmLeaf immtype, string asm,
12180 : BaseTwoOperandRegImm<size, 0b0, 0b0, {0,0,?,?}, regtype, immtype, asm,
12190 multiclass ComparisonOp<bit isUnsigned, bit isMin, string asm,
12192 def Wrr : BaseComparisonOpReg<0b0, isUnsigned, isMin, GPR32, asm, OpNode>;
12196 !not(isUnsigned) : simm8_32b), asm, OpNode>;
12198 def Xrr : BaseComparisonOpReg<0b1, isUnsigned, isMin, GPR64, asm, OpNode>;
12202 !not(isUnsigned) : simm8_64b), asm, OpNode>;
12210 string asm, string operands, string cstr = "">
12211 : I<oops, iops, asm, operands, cstr, []>,
12230 dag oops, dag iops, string asm,
12232 : BaseLRCPC3<size, /*V*/0, opc, oops, iops, asm, operands, cstr> {
12239 string asm, string operands, string cstr>
12240 : BaseLRCPC3<size, /*V*/0, opc, oops, iops, asm, operands, cstr> {
12245 dag oops, dag iops, string asm> {
12246 def i : BaseLRCPC3<size, /*V*/1, opc, oops, iops, asm, "\t$Rt, [$Rn{, $simm}]", /*cstr*/""> {
12251 def a : InstAlias<asm # "\t$Rt, [$Rn]",
12255 class LRCPC3NEONLdStSingle<bit L, dag oops, dag iops, string asm, string cst>
12256 : BaseSIMDLdStSingle<L, /*R*/0b0, /*opcode*/0b100, asm,
12304 class BaseRCWCASEncoding<dag oops, dag iops, string asm>
12305 : I<oops, iops, asm, "\t$Rs, $Rt, [$Rn]", "$out = $Rs", []>,
12388 class BaseRCWOPEncoding<string asm>
12389 : I<(outs GPR64:$Rt),(ins GPR64:$Rs, GPR64sp:$Rn), asm,
12418 class BaseRCWOPPEncoding<string asm>
12420 (ins GPR64common:$Rt, GPR64common:$Rt2, GPR64sp:$Rn), asm,
12471 class LSE128Base<bits<3> op0, bits<2> AR, bit o3, string asm>
12474 asm, "\t$Rt, $Rt2, [$Rn]",
12504 class RtSystemI128<bit L, dag oops, dag iops, string asm, string operands, list<dag> pattern = []> :
12505 RtSystemI<L, oops, iops, asm, operands, pattern> {
12509 class BaseSYSPEncoding<bit L, string asm, string operands, dag outputs, dag inputs>
12510 : RtSystemI128<L, outputs, inputs, asm, operands> {
12521 class SystemPXtI<bit L, string asm> :
12522 BaseSYSPEncoding<L, asm, "\t$op1, $Cn, $Cm, $op2, $Rt", (outs),
12546 class BaseAddSubCPA<bit isSub, string asm> : I<(outs GPR64sp:$Rd),
12548 asm, "\t$Rd, $Rn, $Rm$shift_imm", "", []>, Sched<[]> {
12564 class AddSubCPAAlias<string asm, Instruction inst>
12565 : InstAlias<asm#"\t$Rd, $Rn, $Rm",
12568 multiclass AddSubCPA<bit isSub, string asm> {
12569 def _shift : BaseAddSubCPA<isSub, asm>;
12570 def _noshift : AddSubCPAAlias<asm, !cast<Instruction>(NAME#"_shift")>;
12573 class MulAccumCPA<bit isSub, string asm>
12574 : BaseMulAccum<isSub, 0b011, GPR64, GPR64, asm, []>, Sched<[]> {