567                            SDValue N1) const override;
580                                      unsigned Depth = 0) const override;
585                                            unsigned Depth) const override;
587   MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override {
597                                     TargetLoweringOpt &TLO) const override;
599   MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
606       unsigned *Fast = nullptr) const override;
611                                       unsigned *Fast = nullptr) const override;
614   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
616   const char *getTargetNodeName(unsigned Opcode) const override;
618   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
623                            const TargetLibraryInfo *libInfo) const override;
625   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
628                     bool ForCodeSize) const override;
632   bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
636   bool isVectorClearMaskLegal(ArrayRef<int> M, EVT VT) const override;
640                          EVT VT) const override;
669                               MachineBasicBlock *MBB) const override;
673                           unsigned Intrinsic) const override;
676                              EVT NewVT) const override;
678   bool shouldRemoveRedundantExtend(SDValue Op) const override;
680   bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
681   bool isTruncateFree(EVT VT1, EVT VT2) const override;
683   bool isProfitableToHoist(Instruction *I) const override;
685   bool isZExtFree(Type *Ty1, Type *Ty2) const override;
686   bool isZExtFree(EVT VT1, EVT VT2) const override;
687   bool isZExtFree(SDValue Val, EVT VT2) const override;
690                           SmallVectorImpl<Use *> &Ops) const override;
693       Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override;
695   bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override;
697   unsigned getMaxSupportedInterleaveFactor() const override { return 4; }  in getMaxSupportedInterleaveFactor()
702                             unsigned Factor) const override;
704                              unsigned Factor) const override;
707                                         LoadInst *LI) const override;
710                                        StoreInst *SI) const override;
712   bool isLegalAddImmediate(int64_t) const override;
713   bool isLegalAddScalableImmediate(int64_t) const override;
714   bool isLegalICmpImmediate(int64_t) const override;
717                                    SDValue ConstNode) const override;
719   bool shouldConsiderGEPOffsetSplit() const override;
722                           const AttributeList &FuncAttributes) const override;
725                          const AttributeList &FuncAttributes) const override;
731                              Instruction *I = nullptr) const override;
734                                          int64_t MaxOffset) const override;
740                                   EVT VT) const override;
741   bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
744                                      CodeGenOptLevel OptLevel) const override;
746   const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
747   ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
751                                      CombineLevel Level) const override;
753   bool isDesirableToPullExtFromShl(const MachineInstr &MI) const override {  in isDesirableToPullExtFromShl()
758   bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;
762                                          CombineLevel Level) const override;
765                                             EVT VT) const override;
770                                          Type *Ty) const override;
775                                unsigned Index) const override;
778                             bool MathUsed) const override {  in shouldFormOverflowOp()
785                         AtomicOrdering Ord) const override;
787                               AtomicOrdering Ord) const override;
789   void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override;
794   bool shouldInsertFencesForAtomic(const Instruction *I) const override;
796   shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const override;
799   shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
801   shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
803   shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
806   shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
808   bool useLoadStackGuardNode() const override;
810   getPreferredVectorAction(MVT VT) const override;
814   Value *getIRStackGuard(IRBuilderBase &IRB) const override;
816   void insertSSPDeclarations(Module &M) const override;
817   Value *getSDagStackGuard(const Module &M) const override;
818   Function *getSSPStackGuardCheck(const Module &M) const override;
822   Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
827   getExceptionPointerRegister(const Constant *PersonalityFn) const override {  in getExceptionPointerRegister()
835   getExceptionSelectorRegister(const Constant *PersonalityFn) const override {  in getExceptionSelectorRegister()
840   bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
843                         const MachineFunction &MF) const override {  in canMergeStoresTo()
854   bool isCheapToSpeculateCttz(Type *) const override {  in isCheapToSpeculateCttz()
858   bool isCheapToSpeculateCtlz(Type *) const override {  in isCheapToSpeculateCtlz()
862   bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
864   bool hasAndNotCompare(SDValue V) const override {  in hasAndNotCompare()
869   bool hasAndNot(SDValue Y) const override {  in hasAndNot()
883       SelectionDAG &DAG) const override;
887                                      unsigned ExpansionFactor) const override;
890                                             unsigned KeptBits) const override {  in shouldTransformSignedTruncationCheck()
906   bool preferIncOfAddToSubOfNot(EVT VT) const override;
908   bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
910   bool shouldExpandCmpUsingSelects() const override { return true; }  in shouldExpandCmpUsingSelects()
912   bool isComplexDeinterleavingSupported() const override;
914       ComplexDeinterleavingOperation Operation, Type *Ty) const override;
919       Value *Accumulator = nullptr) const override;
921   bool supportSplitCSR(MachineFunction *MF) const override {  in supportSplitCSR()
925   void initializeSplitCSR(MachineBasicBlock *Entry) const override;
928       const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
930   bool supportSwiftError() const override {  in supportSwiftError()
934   bool supportPtrAuthBundles() const override { return true; }  in supportPtrAuthBundles()
936   bool supportKCFIBundles() const override { return true; }  in supportKCFIBundles()
940                               const TargetInstrInfo *TII) const override;
943   bool enableAggressiveFMAFusion(EVT VT) const override;
946   unsigned getVaListSizeInBits(const DataLayout &DL) const override;
960     const Instruction &I) const override;
964       const DataLayout &DL) const override;
967   bool needsFixedCatchObjects() const override;
969   bool fallBackToDAGISel(const Instruction &Inst) const override;
977   bool mergeStoresAfterLegalization(EVT VT) const override;
990                              bool AllowUnknown = false) const override;
992   bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override;
994   bool shouldExpandCttzElements(EVT VT) const override;
1004   bool isVScaleKnownToBeAPowerOfTwo() const override { return true; }  in isVScaleKnownToBeAPowerOfTwo()
1013                                     EVT VT) const override;
1016                                          EVT VT) const override;
1021                                                 MVT &RegisterVT) const override;
1024   bool hasInlineStackProbe(const MachineFunction &MF) const override;
1027   void verifyTargetSDNode(const SDNode *N) const override;
1038   bool isExtFreeImpl(const Instruction *Ext) const override;
1045   bool shouldExpandBuildVectorWithShuffles(EVT, unsigned) const override;
1051                                SmallVectorImpl<SDValue> &InVals) const override;
1054                                      SDNode *Node) const override;
1057                     SmallVectorImpl<SDValue> &InVals) const override;
1097                       LLVMContext &Context) const override;
1102                       SelectionDAG &DAG) const override;
1247                         SmallVectorImpl<SDNode *> &Created) const override;
1249                         SmallVectorImpl<SDNode *> &Created) const override;
1252                           bool Reciprocal) const override;
1254                            int &ExtraSteps) const override;
1256                            const DenormalMode &Mode) const override;
1258                                       SelectionDAG &DAG) const override;
1259   unsigned combineRepeatedFPDivisors() const override;
1261   ConstraintType getConstraintType(StringRef Constraint) const override;
1263                              const MachineFunction &MF) const override;
1269                                  const char *constraint) const override;
1273                                StringRef Constraint, MVT VT) const override;
1275   const char *LowerXConstraint(EVT ConstraintVT) const override;
1279                                     SelectionDAG &DAG) const override;
1282   getInlineAsmMemConstraint(StringRef ConstraintCode) const override {  in getInlineAsmMemConstraint()
1295                                       SelectionDAG &DAG) const override;
1297   bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override;
1298   bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
1299   bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
1300   bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1301   bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1306                                  SelectionDAG &DAG) const override;
1309                                   SelectionDAG &DAG) const override;
1311                        bool IsPre, MachineRegisterInfo &MRI) const override;
1314                           SelectionDAG &DAG) const override;
1321   bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
1323   void finalizeLowering(MachineFunction &MF) const override;
1326                       const TargetTransformInfo *TTI) const override;
1333                                          unsigned Depth) const override;
1335   bool isTargetCanonicalConstantNode(SDValue Op) const override;
1354   bool preferScalarizeSplat(SDNode *N) const override;
1356   unsigned getMinimumJumpTableEntries() const override;
1358   bool softPromoteHalfType() const override { return true; }  in softPromoteHalfType()