Lines Matching +full:conditional +full:- +full:select
1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
52 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
94 BRCOND, // Conditional branch instruction; "b.cond".
96 CSINV, // Conditional select invert.
97 CSNEG, // Conditional select negate.
98 CSINC, // Conditional select increment.
177 // Conditional compares. Operands: left,right,falsecc,cc,flags
185 // Scalar-to-vector duplication
206 // Vector bitwise select: similar to ISD::VSELECT but not all bits within an
268 // Vector across-lanes addition
287 // Vector across-lanes min/max
304 // Compare-and-branch
320 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
322 /// generated to compensate for the byte-swapping. But sometimes we do
323 /// need to re-interpret the data in SIMD vector registers in big-endian
351 // Floating-point reductions.
378 // Nodes to build an LD64B / ST64B 64-bit quantity out of i64, and vice versa
434 // Non-temporal gather loads
453 // Non-temporal scatter store
463 // Asserts that a function argument (i32) is zero-extended to i8 by
467 // 128-bit system register accesses
473 // Strict (exception-raising) floating point comparison
481 // NEON Load/Store with post-increment base updates
564 /// Control the following reassociation of operands: (op (op x, c1), y) -> (op
589 // *DAG* representation of pointers will always be 64-bits. They will be
590 // truncated and extended when transferred to memory, but the 64-bit DAG
634 /// Similar to isShuffleMaskLegal. Return true is the given 'select with zero'
895 auto VTIsOk = [](EVT VT) -> bool { in shouldTransformSignedTruncationCheck()
922 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && in supportSplitCSR()
923 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); in supportSplitCSR()
1337 // With the exception of data-predicate transitions, no instructions are