727   if (Subtarget->hasFullFP16()) {  in AArch64TargetLowering()
855   if (!Subtarget->hasFullFP16()) {  in AArch64TargetLowering()
876     if (Subtarget->hasFullFP16())  in AArch64TargetLowering()
885     if (Subtarget->hasFullFP16())  in AArch64TargetLowering()
1224     if (Subtarget->hasFullFP16()) {  in AArch64TargetLowering()
1294       if (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()) {  in AArch64TargetLowering()
1355       if (Subtarget->hasFullFP16())  in AArch64TargetLowering()
1364       if (Subtarget->hasFullFP16())  in AArch64TargetLowering()
1862        Subtarget->hasFullFP16()))  in addTypeForNEON()
1911       (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()))  in addTypeForNEON()
3440   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in emitStrictFPComparison()
3458   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in emitComparison()
3567   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in emitConditionalComparison()
4389   if ((InVT.getVectorElementType() == MVT::f16 && !Subtarget->hasFullFP16()) ||  in LowerVectorFP_TO_INT()
4463   if ((SrcVal.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) ||  in LowerFP_TO_INT()
4512        (!Subtarget->hasFullFP16() || DstElementWidth > 16)) ||  in LowerVectorFP_TO_INT_SAT()
4582   if ((SrcVT == MVT::f16 && !Subtarget->hasFullFP16()) || SrcVT == MVT::bf16) {  in LowerFP_TO_INT_SAT()
4592        (SrcVT == MVT::f16 && Subtarget->hasFullFP16())) &&  in LowerFP_TO_INT_SAT()
4855   if (Op.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) {  in LowerINT_TO_FP()
10445   if ((LHS.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) ||  in LowerSELECT_CC()
10767   if ((Ty == MVT::f16 || Ty == MVT::bf16) && !Subtarget->hasFullFP16()) {  in LowerSELECT()
10776   if ((Ty == MVT::f16 || Ty == MVT::bf16) && !Subtarget->hasFullFP16()) {  in LowerSELECT()
11286         (Subtarget->hasFullFP16() && AArch64_AM::getFP16Imm(ImmInt) != -1) ||  in isFPImmLegal()
13934         (ST->hasFullFP16() && (R = TryWithFNeg(DefBits, MVT::f16))))  in ConstantBuildVector()
15111   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in LowerVSETCC()
16035           !Subtarget->hasFullFP16())  in shouldSinkOperands()
17444     return Subtarget->hasFullFP16();  in isFMAFasterThanFMulAndFAdd()
18604       (FloatBits != 16 || !Subtarget->hasFullFP16()))  in performFpToIntCombine()
19247   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in performExtractVectorEltCombine()
25858       (VT.getScalarType() == MVT::f16 && !Subtarget->hasFullFP16()) ||  in ReplaceAddWithADDP()
26929   if (FPVT == MVT::v8f16 && !Subtarget->hasFullFP16())  in shouldConvertFpToSat()
28507   return (ScalarTy->isHalfTy() && Subtarget->hasFullFP16()) ||  in isComplexDeinterleavingOperationSupported()