2634     MAKE_CASE(AArch64ISD::ZIP1)  in getTargetNodeName()
5777     return DAG.getNode(AArch64ISD::ZIP1, dl, Op.getValueType(),  in LowerINTRINSIC_WO_CHAIN()
12835     return DAG.getNode(AArch64ISD::ZIP1, dl, VT, OpLHS, OpRHS);  in GeneratePerfectShuffle()
13134                         DAG.getNode(AArch64ISD::ZIP1, dl, SrcVT, SrcOp, Zeros));  in LowerZERO_EXTEND_VECTOR_INREG()
13234     unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;  in LowerVECTOR_SHUFFLE()
13247     unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;  in LowerVECTOR_SHUFFLE()
19484   if (N->getNumOperands() == 2 && N0Opc == AArch64ISD::ZIP1 &&  in performConcatVectorsCombine()
19491     return DAG.getNode(AArch64ISD::ZIP1, dl, VT, E0, E1);  in performConcatVectorsCombine()
22807     SDValue Zipped = DAG.getNode(AArch64ISD::ZIP1, DL, VecVT,  in vectorToScalarBitmask()
27957   SDValue Lo = DAG.getNode(AArch64ISD::ZIP1, DL, OpVT, Op.getOperand(0),  in LowerVECTOR_INTERLEAVE()
28258         DAG, VT, DAG.getNode(AArch64ISD::ZIP1, DL, ContainerVT, Op1, Op2));  in LowerFixedLengthVECTOR_SHUFFLEToSVE()
28268         DAG, VT, DAG.getNode(AArch64ISD::ZIP1, DL, ContainerVT, Op1, Op1));  in LowerFixedLengthVECTOR_SHUFFLEToSVE()
28751   case AArch64ISD::ZIP1:  in verifyTargetSDNode()