2765     MAKE_CASE(AArch64ISD::UUNPKLO)  in getTargetNodeName()
5744     return DAG.getNode(AArch64ISD::UUNPKLO, dl, Op.getValueType(),  in LowerINTRINSIC_WO_CHAIN()
14629       SDValue LoVec0 = DAG.getNode(AArch64ISD::UUNPKLO, DL, WideVT, Vec0);  in LowerINSERT_SUBVECTOR()
14721   unsigned UnpkLo = Signed ? AArch64ISD::SUNPKLO : AArch64ISD::UUNPKLO;  in LowerDIV()
18891   if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) {  in performSVEAndCombine()
22019           N->getOpcode() == AArch64ISD::UUNPKLO) &&  in performUnpackCombine()
22030       N->getOpcode() == AArch64ISD::UUNPKLO) {  in performUnpackCombine()
22097   if (Lo.getOpcode() != AArch64ISD::UUNPKLO &&  in tryCombineExtendRShTrunc()
22213   if (Op0.getOpcode() == AArch64ISD::UUNPKLO) {  in performUzpCombine()
24729   if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) {  in performSignExtendInRegCombine()
25369   case AArch64ISD::UUNPKLO:  in PerformDAGCombine()
25940   unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI;  in ReplaceExtractSubVectorResults()
27462   unsigned ExtendOpc = Signed ? AArch64ISD::SUNPKLO : AArch64ISD::UUNPKLO;  in LowerFixedLengthVectorIntExtendToSVE()
28732   case AArch64ISD::UUNPKLO:  in verifyTargetSDNode()