Lines Matching refs:EXTLOAD

1029     setLoadExtAction(ISD::EXTLOAD, VT, MVT::bf16, Expand);  in AArch64TargetLowering()
1030 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in AArch64TargetLowering()
1031 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in AArch64TargetLowering()
1032 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in AArch64TargetLowering()
1033 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); in AArch64TargetLowering()
1343 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Custom); in AArch64TargetLowering()
1383 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i8, Custom); in AArch64TargetLowering()
1408 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1554 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1565 for (auto Op : {ISD::ZEXTLOAD, ISD::SEXTLOAD, ISD::EXTLOAD}) { in AArch64TargetLowering()
1882 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand); in addTypeForNEON()
2014 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Default); in addTypeForFixedLengthSVE()
2026 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Default); in addTypeForFixedLengthSVE()
6254 ExtType = ISD::EXTLOAD; in LowerMGATHER()
6574 LoadNode->getExtensionType() == ISD::EXTLOAD) in LowerLOAD()
7488 ExtType = ISD::EXTLOAD; in LowerFormalArguments()
18921 MaskedLoadOp->getExtensionType() == ISD::EXTLOAD)) { in performSVEAndCombine()
24988 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, in performFPExtendCombine()
27249 if (VT.isFloatingPoint() && Load->getExtensionType() == ISD::EXTLOAD) { in LowerFixedLengthVectorLoadToSVE()