Lines Matching refs:CCVal
4090 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32); in LowerXOR() local
4092 CCVal, Overflow); in LowerXOR()
4134 SDValue CCVal; in LowerXOR() local
4135 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl); in LowerXOR()
4142 CCVal, Cmp); in LowerXOR()
4230 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32); in LowerXALUO() local
4232 CCVal, Overflow); in LowerXALUO()
6619 SDValue CCVal = DAG.getConstant(CC, dl, MVT::i32); in LowerBRCOND() local
6620 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBRCOND()
9842 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32); in LowerBR_CC() local
9844 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBR_CC()
9909 SDValue CCVal; in LowerBR_CC() local
9910 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl); in LowerBR_CC()
9911 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBR_CC()
10342 SDValue CCVal; in LowerSETCC() local
10344 LHS, RHS, ISD::getSetCCInverse(CC, LHS.getValueType()), CCVal, DAG, dl); in LowerSETCC()
10349 SDValue Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp); in LowerSETCC()
10416 SDValue CCVal = in LowerSETCCCARRY() local
10420 return DAG.getNode(AArch64ISD::CSEL, DL, OpVT, FVal, TVal, CCVal, in LowerSETCCCARRY()
10599 SDValue CCVal; in LowerSELECT_CC() local
10600 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl); in LowerSELECT_CC()
10602 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp); in LowerSELECT_CC()
10702 SDValue CCVal = Op->getOperand(0); in LowerSELECT() local
10712 DAG.getNode(ISD::SELECT, DL, MVT::nxv16i1, CCVal, TVal, FVal); in LowerSELECT()
10718 SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, CCVal); in LowerSELECT()
10728 SDValue SplatVal = DAG.getSExtOrTrunc(CCVal, DL, SplatValVT); in LowerSELECT()
10735 if (ISD::isOverflowIntrOpRes(CCVal)) { in LowerSELECT()
10737 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0))) in LowerSELECT()
10742 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG); in LowerSELECT()
10743 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32); in LowerSELECT() local
10746 CCVal, Overflow); in LowerSELECT()
10752 if (CCVal.getOpcode() == ISD::SETCC) { in LowerSELECT()
10753 LHS = CCVal.getOperand(0); in LowerSELECT()
10754 RHS = CCVal.getOperand(1); in LowerSELECT()
10755 CC = cast<CondCodeSDNode>(CCVal.getOperand(2))->get(); in LowerSELECT()
10757 LHS = CCVal; in LowerSELECT()
10758 RHS = DAG.getConstant(0, DL, CCVal.getValueType()); in LowerSELECT()
17991 SDValue CCVal, CSNeg; in BuildSREMPow2() local
17993 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETGE, CCVal, DAG, DL); in BuildSREMPow2()
17995 CSNeg = DAG.getNode(AArch64ISD::CSNEG, DL, VT, And, And, CCVal, Cmp); in BuildSREMPow2()
18000 SDValue CCVal = DAG.getConstant(AArch64CC::MI, DL, MVT_CC); in BuildSREMPow2() local
18006 CSNeg = DAG.getNode(AArch64ISD::CSNEG, DL, VT, AndPos, AndNeg, CCVal, in BuildSREMPow2()
19824 SDValue CCVal; in performSetccAddFolding() local
19828 CCVal = DAG.getConstant( in performSetccAddFolding()
19835 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, CmpVT), CCVal, DAG, in performSetccAddFolding()
19840 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp); in performSetccAddFolding()
19949 SDValue CCVal = DAG.getConstant(AArch64CC, DL, MVT::i32); in performAddCSelIntoCSinc() local
19952 return DAG.getNode(AArch64ISD::CSINC, DL, VT, NewNode, RHS, CCVal, Cmp); in performAddCSelIntoCSinc()
23641 SDValue CCVal = N->getOperand(2); in performBRCONDCombine() local
23644 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!"); in performBRCONDCombine()
23645 unsigned CC = CCVal->getAsZExtVal(); in performBRCONDCombine()