Lines Matching full:cc2
9924 AArch64CC::CondCode CC1, CC2; in LowerBR_CC() local
9925 changeFPCCToAArch64CC(CC, CC1, CC2); in LowerBR_CC()
9929 if (CC2 != AArch64CC::AL) { in LowerBR_CC()
9930 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32); in LowerBR_CC()
10368 AArch64CC::CondCode CC1, CC2; in LowerSETCC() local
10369 changeFPCCToAArch64CC(CC, CC1, CC2); in LowerSETCC()
10371 if (CC2 == AArch64CC::AL) { in LowerSETCC()
10373 CC2); in LowerSETCC()
10391 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32); in LowerSETCC()
10617 AArch64CC::CondCode CC1, CC2; in LowerSELECT_CC() local
10618 changeFPCCToAArch64CC(CC, CC1, CC2); in LowerSELECT_CC()
10644 if (CC2 != AArch64CC::AL) { in LowerSELECT_CC()
10645 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32); in LowerSELECT_CC()
15133 AArch64CC::CondCode CC1, CC2; in LowerVSETCC() local
15135 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert); in LowerVSETCC()
15143 if (CC2 != AArch64CC::AL) { in LowerVSETCC()
15145 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG); in LowerVSETCC()
23733 // (CSEL l r EQ (CMP (CSEL x y cc2 cond) x)) => (CSEL l r cc2 cond)
23734 // (CSEL l r EQ (CMP (CSEL x y cc2 cond) y)) => (CSEL l r !cc2 cond)
23737 // (CSEL l r NE (CMP (CSEL x y cc2 cond) x)) => (CSEL l r !cc2 cond)
23738 // (CSEL l r NE (CMP (CSEL x y cc2 cond) y)) => (CSEL l r cc2 cond)