382                             unsigned Opc_rr, unsigned Opc_ri,
386                                        unsigned Opc_rr);
428                              unsigned Opc_rr, unsigned Opc_ri);
430   findAddrModeSVELoadStore(SDNode *N, unsigned Opc_rr, unsigned Opc_ri,
1743 AArch64DAGToDAGISel::findAddrModeSVELoadStore(SDNode *N, unsigned Opc_rr,  in findAddrModeSVELoadStore()  argument
1760   return std::make_tuple(IsRegReg ? Opc_rr : Opc_ri, NewBase, NewOffset);  in findAddrModeSVELoadStore()
1917                                                unsigned Opc_rr, bool IsIntr) {  in SelectPredicatedLoad()  argument
1927       N, Opc_rr, Opc_ri, N->getOperand(IsIntr ? 3 : 2),  in SelectPredicatedLoad()
1952                                                           unsigned Opc_rr) {  in SelectContiguousMultiVectorLoad()  argument
1963       findAddrModeSVELoadStore(N, Opc_rr, Opc_ri, Base, Offset, Scale);  in SelectContiguousMultiVectorLoad()
2189                                                 unsigned Scale, unsigned Opc_rr,  in SelectPredicatedStore()  argument
2201       N, Opc_rr, Opc_ri, N->getOperand(NumVecs + 3),  in SelectPredicatedStore()