Lines Matching +full:sb +full:- +full:rmi
1 //=- AArch64Features.td - Describe AArch64 SubtargetFeatures -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
17 string TargetFeatureName, // String used for -target-feature, unless overridden.
28 // The user visible name used by -march/-mcpu modifiers and target attribute
37 // An Extension that can be toggled via a '-march'/'-mcpu' modifier or a target
40 …string TargetFeatureName, // String used for -target-feature and -march, unless overrid…
47 // used for -target-feature. However, there are exceptions. Therefore we
62 //===----------------------------------------------------------------------===//
64 //===----------------------------------------------------------------------===//
67 def FeatureFPARMv8 : ExtensionWithMArch<"fp-armv8", "FPARMv8", "FEAT_FP",
68 "Enable Armv8.0-A Floating Point Extensions">;
92 "Enable Armv8.0-A CRC-32 checksum instructions">;
99 "Enable Armv8.0-A PMUv3 Performance Monitors extension">;
104 //===----------------------------------------------------------------------===//
106 //===----------------------------------------------------------------------===//
109 "Enable Armv8.1-A Large System Extension (LSE) atomic instructions">;
113 "Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions",
117 "Enable Armv8.1-A Privileged Access-Never extension">;
120 "Enable Armv8.1-A Limited Ordering Regions extension">;
126 "Enable Armv8.1-A Virtual Host extension", [FeatureCONTEXTIDREL2]>;
128 //===----------------------------------------------------------------------===//
130 //===----------------------------------------------------------------------===//
139 "Enable Armv8.0-A Reliability, Availability and Serviceability Extensions">;
143 "Enable half-precision floating-point data processing", [FeatureFPARMv8]>;
149 def FeaturePAN_RWV : Extension<"pan-rwv", "PAN_RWV", "FEAT_PAN2",
150 "Enable Armv8.2-A PAN s1e1R and s1e1W Variants", [FeaturePAN]>;
153 "Enable Armv8.2-A UAO PState">;
156 "Enable Armv8.2-A data Cache Clean to Point of Persistence">;
173 //===----------------------------------------------------------------------===//
175 //===----------------------------------------------------------------------===//
181 "Enable Armv8.3-A Pointer Authentication extension">;
185 "Enable Armv8.3-A JavaScript FP conversion instructions",
189 "Enable v8.3-A Pointer Authentication Faulting enhancement">;
192 "Enable Armv8.3-A Extend of the CCSIDR number of sets">;
196 "Enable Armv8.3-A Floating-point complex number support",
200 "Enable Armv8.4-A Nested Virtualization Enchancement">;
202 //===----------------------------------------------------------------------===//
204 //===----------------------------------------------------------------------===//
207 "Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules">;
216 "Enable Armv8.4-A Memory system Partitioning and Monitoring extension">;
219 "Enable Armv8.4-A Data Independent Timing instructions">;
222 "Enable Armv8.4-A Trace extension">;
225 "Enable Armv8.4-A Activity Monitors extension">;
228 "Enable Armv8.4-A Secure Exception Level 2 extension">;
230 def FeatureTLB_RMI : Extension<"tlb-rmi", "TLB_RMI",
232 "Enable Armv8.4-A TLB Range and Maintenance instructions">;
235 "Enable Armv8.4-A Flag Manipulation instructions">;
237 def FeatureRCPC_IMMO : Extension<"rcpc-immo", "RCPC_IMMO", "FEAT_LRCPC2",
238 "Enable Armv8.4-A RCPC instructions with Immediate Offsets",
241 //===----------------------------------------------------------------------===//
243 //===----------------------------------------------------------------------===//
249 "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
250 "an integer (in FP format) forcing it to fit into a 32- or 64-bit int">;
252 def FeatureSB : ExtensionWithMArch<"sb", "SB", "FEAT_SB",
253 "Enable Armv8.5-A Speculation Barrier">;
259 "Enable Armv8.5-A execution and data prediction invalidation instructions">;
262 "Enable Armv8.5-A Cache Clean to Point of Deep Persistence">;
271 // NOTE: "memtag" means FEAT_MTE + FEAT_MTE2 for -march or
277 //===----------------------------------------------------------------------===//
279 //===----------------------------------------------------------------------===//
285 "Enable Armv8.6-A Activity Monitors Virtualization support",
295 //===----------------------------------------------------------------------===//
297 //===----------------------------------------------------------------------===//
300 "Enable Armv8.7-A limited-TLB-maintenance instruction">;
303 "Enable Armv8.7-A WFET and WFIT instruction">;
306 "Enable Armv8.7-A HCRX_EL2 system register">;
310 "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
312 def FeatureSPE_EEF : Extension<"spe-eef", "SPE_EEF", "FEAT_SPEv1p2",
315 //===----------------------------------------------------------------------===//
317 //===----------------------------------------------------------------------===//
320 "Enable Armv8.8-A Hinted Conditional Branches Extension">;
323 "Enable Armv8.8-A memcpy and memset acceleration instructions">;
326 "Enable Armv8.8-A Non-maskable Interrupts">;
328 //===----------------------------------------------------------------------===//
330 //===----------------------------------------------------------------------===//
333 "Enable Armv8.9-A Reliability, Availability and Serviceability Extensions",
342 def FeaturePRFM_SLC : Extension<"prfm-slc-target", "PRFM_SLC", "FEAT_PRFMSLC",
351 "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set",
355 "Enable Armv8.9-A Translation Hardening Extension">;
357 //===----------------------------------------------------------------------===//
359 //===----------------------------------------------------------------------===//
361 def FeatureUseFixedOverScalableIfEqualCost: SubtargetFeature<"use-fixed-over-scalable-if-equal-cost…
363 "Prefer fixed width loop vectorization over scalable if the cost-model assigns equal costs">;
365 def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
372 def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
376 def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4", "FEAT_SVE_SM4",
379 def FeatureSVE2SHA3 : ExtensionWithMArch<"sve2-sha3", "SVE2SHA3", "FEAT_SVE_SHA3",
382 def FeatureSVE2BitPerm : ExtensionWithMArch<"sve2-bitperm", "SVE2BitPerm",
395 //===----------------------------------------------------------------------===//
397 //===----------------------------------------------------------------------===//
399 //===----------------------------------------------------------------------===//
401 //===----------------------------------------------------------------------===//
412 def FeatureSMEF64F64 : ExtensionWithMArch<"sme-f64f64", "SMEF64F64", "FEAT_SME_F64F64",
415 def FeatureSMEI16I64 : ExtensionWithMArch<"sme-i16i64", "SMEI16I64", "FEAT_SME_I16I64",
418 def FeatureSMEFA64 : ExtensionWithMArch<"sme-fa64", "SMEFA64", "FEAT_SME_FA64",
421 //===----------------------------------------------------------------------===//
423 //===----------------------------------------------------------------------===//
431 //===----------------------------------------------------------------------===//
433 //===----------------------------------------------------------------------===//
439 "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions", [FeatureBF16]>;
442 // {FeatureB16B16, FeatureSME2} respectively. This allows LLVM-20 interfacing programs
443 // that use '+sve-b16b16' and '+sme-b16b16' to compile in LLVM-19.
444 def FeatureSVEB16B16 : ExtensionWithMArch<"sve-b16b16", "SVEB16B16", "FEAT_SVE_B16B16",
445 …"Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions", [FeatureB16B16…
447 def FeatureSMEB16B16 : ExtensionWithMArch<"sme-b16b16", "SMEB16B16", "FEAT_SME_B16B16",
448 "Enable SME2.1 ZA-targeting non-widening BFloat16 instructions", [FeatureSME2, FeatureB16B16]>;
450 def FeatureSMEF16F16 : ExtensionWithMArch<"sme-f16f16", "SMEF16F16", "FEAT_SME_F16F16",
451 "Enable SME non-widening Float16 instructions", [FeatureSME2]>;
457 "Enable Armv8.0-A Check Feature Status Extension">;
460 "Enable Armv9.4-A Guarded Call Stack Extension", [FeatureCHK]>;
463 "Enable Armv9.4-A Instrumentation Extension", [FeatureETE, FeatureTRBE]>;
466 "Enable Armv9.4-A 128-bit Atomic instructions",
473 "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers "
477 //===----------------------------------------------------------------------===//
479 //===----------------------------------------------------------------------===//
491 "Enable Armv9.5-A FP8 multiply-add instructions", [FeatureFP8]>;
493 def FeatureSSVE_FP8FMA : ExtensionWithMArch<"ssve-fp8fma", "SSVE_FP8FMA", "FEAT_SSVE_FP8FMA",
494 "Enable SVE2 FP8 multiply-add instructions", [FeatureSME2, FeatureFP8]>;
497 "Enable FP8 4-way dot instructions", [FeatureFP8FMA]>;
500 "Enable FP8 2-way dot instructions", [FeatureFP8DOT4]>;
502 def FeatureSSVE_FP8DOT4 : ExtensionWithMArch<"ssve-fp8dot4", "SSVE_FP8DOT4", "FEAT_SSVE_FP8DOT4",
503 "Enable SVE2 FP8 4-way dot product instructions", [FeatureSSVE_FP8FMA]>;
505 def FeatureSSVE_FP8DOT2 : ExtensionWithMArch<"ssve-fp8dot2", "SSVE_FP8DOT2", "FEAT_SSVE_FP8DOT2",
506 "Enable SVE2 FP8 2-way dot product instructions", [FeatureSSVE_FP8DOT4]>;
508 def FeatureSME_LUTv2 : ExtensionWithMArch<"sme-lutv2", "SME_LUTv2", "FEAT_SME_LUTv2",
511 def FeatureSMEF8F32 : ExtensionWithMArch<"sme-f8f32", "SMEF8F32", "FEAT_SME_F8F32",
514 def FeatureSMEF8F16 : ExtensionWithMArch<"sme-f8f16", "SMEF8F16", "FEAT_SME_F8F16",
518 "Enable Armv9.5-A Checked Pointer Arithmetic">;
520 def FeaturePAuthLR : ExtensionWithMArch<"pauth-lr", "PAuthLR", "FEAT_PAuth_LR",
521 "Enable Armv9.5-A PAC enhancements">;
524 "Enable Armv9.5-A TLBI VMALL for Dirty State">;
526 //===----------------------------------------------------------------------===//
528 //===----------------------------------------------------------------------===//
530 def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
546 // merging-predication.
548 : SubtargetFeature<"use-experimental-zeroing-pseudos",
554 def FeatureNoSVEFPLD1R : SubtargetFeature<"no-sve-fp-ld1r",
558 "Has zero-cycle register moves">;
560 def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
561 … "Has zero-cycle zeroing instructions for generic registers">;
567 def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false",
568 "Has no zero-cycle zeroing instructions for FP registers">;
571 "Has zero-cycle zeroing instructions",
574 /// ... but the floating-point version doesn't quite work in rare cases on older
576 def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
578 "The zero-cycle floating-point zeroing instruction has a bug">;
580 def FeatureStrictAlign : SubtargetFeature<"strict-align",
585 foreach i = {1-7,9-15,18,20-28} in
586 def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
590 def FeatureReserveLRForRA : SubtargetFeature<"reserve-lr-for-ra",
594 foreach i = {8-15,18} in
595 def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
598 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
600 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
603 "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
607 "enable-select-opt", "EnableSelectOptimize", "true",
610 def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
614 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
617 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
620 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
623 def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address",
627 def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow",
631 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
635 "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
639 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
643 "cmp-bcc-fusion", "HasCmpBccFusion", "true",
647 "fuse-address", "HasFuseAddress", "true",
651 "fuse-aes", "HasFuseAES", "true",
655 "fuse-arith-logic", "HasFuseArithmeticLogic", "true",
659 "fuse-csel", "HasFuseCCSelect", "true",
663 "fuse-crypto-eor", "HasFuseCryptoEOR", "true",
667 "fuse-adrp-add", "HasFuseAdrpAdd", "true",
671 "fuse-literals", "HasFuseLiterals", "true",
675 "fuse-addsub-2reg-const1", "HasFuseAddSub2RegAndConstOne", "true",
676 "CPU fuses (a + b + 1) and (a - b - 1)">;
679 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
683 "store-pair-suppress", "EnableStorePairSuppress", "true",
687 : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
688 "Force jump table entries to be 32-bits wide except at MinSize">;
691 "use-reciprocal-square-root", "UseRSqrt", "true",
694 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
702 // some old Apple cores (A7-A10?) which handle all shifts slowly. Cortex-A57
703 // and derived designs through Cortex-X1 take an extra micro-op for shifts
711 "addr-lsl-slow-14", "HasAddrLSLSlow14", "true",
715 "alu-lsl-fast", "HasALULSLFast", "true",
719 SubtargetFeature<"aggressive-fma",
722 "Enable Aggressive FMA for floating-point.">;
724 def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
729 def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
738 def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769",
739 "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">;
741 def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",
744 "after a return-twice">;
746 def FeatureDisableLdp : SubtargetFeature<"disable-ldp", "HasDisableLdp",
749 def FeatureDisableStp : SubtargetFeature<"disable-stp", "HasDisableStp",
752 def FeatureLdpAlignedOnly : SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedOnly",
755 def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only", "HasStpAlignedOnly",
758 //===----------------------------------------------------------------------===//
848 // Not mandatory in v8.0-R, but included here on the grounds that it
852 // For v8-R, we do not enable crypto and align with GCC that enables a more
859 //===----------------------------------------------------------------------===//
861 //===----------------------------------------------------------------------===//
863 foreach i = 1-3 in
864 def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",
866 def FeatureUseROEL0ForTP : SubtargetFeature<"tpidrro-el0", "UseROEL0ForTP",
869 //===----------------------------------------------------------------------===//
871 //===----------------------------------------------------------------------===//
873 def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr",
876 def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr",
879 def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat",