Lines Matching +full:0 +full:x17

3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
150 // Emit the sequence to compute a discriminator into x17, or reuse AddrDisc.
264 int64_t Feat00Value = 0; in emitStartOfAsmFile()
290 unsigned Flags = 0; in emitStartOfAsmFile()
384 for (int8_t I = 0; I < NoopsInSledCount; I++) in emitSled()
385 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); in emitSled()
414 .addReg(MI.getOperand(0).getReg()) in LowerPATCHABLE_EVENT_CALL()
415 .addImm(0); in LowerPATCHABLE_EVENT_CALL()
420 .addImm(0); in LowerPATCHABLE_EVENT_CALL()
446 .addImm(0)); in LowerPATCHABLE_EVENT_CALL()
486 Register AddrReg = MI.getOperand(0).getReg(); in LowerKCFI_CHECK()
489 assert(std::next(MI.getIterator())->getOperand(0).getReg() == AddrReg && in LowerKCFI_CHECK()
497 // ScratchRegs[0] and use it for the ESR AddrIndex below. in LowerKCFI_CHECK()
498 AddrReg = getXRegFromWReg(ScratchRegs[0]); in LowerKCFI_CHECK()
503 .addImm(0)); in LowerKCFI_CHECK()
515 assert(ScratchRegs[0] != AddrReg && ScratchRegs[1] != AddrReg && in LowerKCFI_CHECK()
520 int64_t PrefixNops = 0; in LowerKCFI_CHECK()
529 .addReg(ScratchRegs[0]) in LowerKCFI_CHECK()
539 .addImm(Type & 0xFFFF) in LowerKCFI_CHECK()
540 .addImm(0)); in LowerKCFI_CHECK()
544 .addImm((Type >> 16) & 0xFFFF) in LowerKCFI_CHECK()
550 .addReg(ScratchRegs[0]) in LowerKCFI_CHECK()
552 .addImm(0)); in LowerKCFI_CHECK()
560 // The base ESR is 0x8000 and the register information is encoded in bits in LowerKCFI_CHECK()
561 // 0-9 as follows: in LowerKCFI_CHECK()
562 // - 0-4: n, where the register Xn contains the target address in LowerKCFI_CHECK()
564 // Where n, m are in [0, 30]. in LowerKCFI_CHECK()
581 unsigned ESR = 0x8000 | ((TypeIndex & 31) << 5) | (AddrIndex & 31); in LowerKCFI_CHECK()
587 Register Reg = MI.getOperand(0).getReg(); in LowerHWASAN_CHECK_MEMACCESS()
597 uint64_t FixedShadowOffset = IsFixedShadow ? MI.getOperand(2).getImm() : 0; in LowerHWASAN_CHECK_MEMACCESS()
641 unsigned Reg = std::get<0>(P.first); in emitHwasanMemaccessSymbols()
653 (AccessInfo >> HWASanAccessInfo::MatchAllShift) & 0xff; in emitHwasanMemaccessSymbols()
655 1 << ((AccessInfo >> HWASanAccessInfo::AccessSizeShift) & 0xf); in emitHwasanMemaccessSymbols()
661 ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, 0, Sym->getName(), in emitHwasanMemaccessSymbols()
682 .addReg(AArch64::X17) in emitHwasanMemaccessSymbols()
688 .addReg(AArch64::X17) in emitHwasanMemaccessSymbols()
690 .addImm(0) in emitHwasanMemaccessSymbols()
691 .addImm(0), in emitHwasanMemaccessSymbols()
699 .addImm(0) in emitHwasanMemaccessSymbols()
700 .addImm(0), in emitHwasanMemaccessSymbols()
726 .addReg(AArch64::X17) in emitHwasanMemaccessSymbols()
733 .addReg(AArch64::X17) in emitHwasanMemaccessSymbols()
735 .addImm(0), in emitHwasanMemaccessSymbols()
749 .addImm(0), in emitHwasanMemaccessSymbols()
760 .addReg(AArch64::X17) in emitHwasanMemaccessSymbols()
762 .addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)), in emitHwasanMemaccessSymbols()
766 .addReg(AArch64::X17) in emitHwasanMemaccessSymbols()
767 .addReg(AArch64::X17) in emitHwasanMemaccessSymbols()
769 .addImm(0), in emitHwasanMemaccessSymbols()
775 .addImm(0), in emitHwasanMemaccessSymbols()
787 .addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)), in emitHwasanMemaccessSymbols()
792 .addImm(0), in emitHwasanMemaccessSymbols()
829 .addImm(0), in emitHwasanMemaccessSymbols()
835 .addImm(0), in emitHwasanMemaccessSymbols()
1040 if (ExtraCode && ExtraCode[0]) { in PrintAsmOperand()
1041 if (ExtraCode[1] != 0) in PrintAsmOperand()
1044 switch (ExtraCode[0]) { in PrintAsmOperand()
1050 return printAsmMRegister(MO, ExtraCode[0], O); in PrintAsmOperand()
1051 if (MO.isImm() && MO.getImm() == 0) { in PrintAsmOperand()
1052 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR; in PrintAsmOperand()
1066 switch (ExtraCode[0]) { in PrintAsmOperand()
1134 if (ExtraCode && ExtraCode[0] && ExtraCode[0] != 'a') in PrintAsmMemoryOperand()
1154 for (unsigned I = 0, E = std::distance(MI->debug_operands().begin(), in PrintDebugValueComment()
1157 if (I != 0) in PrintDebugValueComment()
1178 for (unsigned JTI = 0, e = JT.size(); JTI != e; ++JTI) { in emitJumpTableInfo()
1230 return std::make_tuple(Base, 0, BranchLabel, EntrySize); in getCodeViewJumpTableInfo()
1259 StringRef NameStr = cast<MDString>(Node->getOperand(0))->getString(); in emitFunctionEntryLabel()
1292 StringRef ExpStr = cast<MDString>(Node->getOperand(0))->getString(); in emitGlobalAlias()
1328 Register DestReg = MI.getOperand(0).getReg(); in LowerJumpTableDest()
1369 .addImm(0) in LowerJumpTableDest()
1370 .addImm(Size == 1 ? 0 : 1)); in LowerJumpTableDest()
1378 .addImm(Size == 4 ? 0 : 2)); in LowerJumpTableDest()
1382 unsigned InstsEmitted = 0; in LowerHardenedBRJumpTable()
1391 // mov x17, #<size of table> ; depending on table size, with MOVKs in LowerHardenedBRJumpTable()
1392 // cmp x16, x17 ; or #imm if table size fits in 12-bit in LowerHardenedBRJumpTable()
1395 // adrp x17, Ltable@PAGE ; materialize table address in LowerHardenedBRJumpTable()
1396 // add x17, Ltable@PAGEOFF in LowerHardenedBRJumpTable()
1397 // ldrsw x16, [x17, x16, lsl #2] ; load table entry in LowerHardenedBRJumpTable()
1400 // adr x17, Lanchor ; compute target address in LowerHardenedBRJumpTable()
1401 // add x16, x17, x16 in LowerHardenedBRJumpTable()
1404 MachineOperand JTOp = MI.getOperand(0); in LowerHardenedBRJumpTable()
1413 // immediate, using x17 as a scratch register. in LowerHardenedBRJumpTable()
1420 .addImm(0)); in LowerHardenedBRJumpTable()
1425 .addReg(AArch64::X17) in LowerHardenedBRJumpTable()
1427 .addImm(0)); in LowerHardenedBRJumpTable()
1433 if ((MaxTableEntry >> Offset) == 0) in LowerHardenedBRJumpTable()
1437 .addReg(AArch64::X17) in LowerHardenedBRJumpTable()
1438 .addReg(AArch64::X17) in LowerHardenedBRJumpTable()
1446 .addReg(AArch64::X17) in LowerHardenedBRJumpTable()
1447 .addImm(0)); in LowerHardenedBRJumpTable()
1451 // This picks entry #0 on failure. in LowerHardenedBRJumpTable()
1472 MCInstBuilder(AArch64::ADRP).addReg(AArch64::X17).addOperand(JTMCHi)); in LowerHardenedBRJumpTable()
1476 .addReg(AArch64::X17) in LowerHardenedBRJumpTable()
1477 .addReg(AArch64::X17) in LowerHardenedBRJumpTable()
1479 .addImm(0)); in LowerHardenedBRJumpTable()
1484 .addReg(AArch64::X17) in LowerHardenedBRJumpTable()
1486 .addImm(0) in LowerHardenedBRJumpTable()
1497 MCInstBuilder(AArch64::ADR).addReg(AArch64::X17).addExpr(AdrLabelE)); in LowerHardenedBRJumpTable()
1502 .addReg(AArch64::X17) in LowerHardenedBRJumpTable()
1504 .addImm(0)); in LowerHardenedBRJumpTable()
1535 int i = 0; in LowerMOPS()
1560 assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!"); in LowerSTACKMAP()
1566 while (NumNOPBytes > 0) { in LowerSTACKMAP()
1577 for (unsigned i = 0; i < NumNOPBytes; i += 4) in LowerSTACKMAP()
1578 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); in LowerSTACKMAP()
1593 unsigned EncodedBytes = 0; in LowerPATCHPOINT()
1595 assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget && in LowerPATCHPOINT()
1602 .addImm((CallTarget >> 32) & 0xFFFF) in LowerPATCHPOINT()
1607 .addImm((CallTarget >> 16) & 0xFFFF) in LowerPATCHPOINT()
1612 .addImm(CallTarget & 0xFFFF) in LowerPATCHPOINT()
1613 .addImm(0)); in LowerPATCHPOINT()
1620 assert((NumBytes - EncodedBytes) % 4 == 0 && in LowerPATCHPOINT()
1623 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); in LowerPATCHPOINT()
1630 assert(PatchBytes % 4 == 0 && "Invalid number of NOP bytes requested!"); in LowerSTATEPOINT()
1631 for (unsigned i = 0; i < PatchBytes; i += 4) in LowerSTATEPOINT()
1632 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); in LowerSTATEPOINT()
1671 Register DefRegister = FaultingMI.getOperand(0).getReg(); in LowerFAULTING_OP()
1688 if (DefRegister != (Register)0) in LowerFAULTING_OP()
1703 Register DestReg = MI.getOperand(0).getReg(); in emitFMov0()
1717 MOVI.addOperand(MCOperand::createImm(0)); in emitFMov0()
1757 // If there's only a constant discriminator, MOV it into x17. in emitPtrauthDiscriminator()
1760 .addReg(AArch64::X17) in emitPtrauthDiscriminator()
1762 .addImm(/*shift=*/0)); in emitPtrauthDiscriminator()
1764 return AArch64::X17; in emitPtrauthDiscriminator()
1767 // If there are both, emit a blend into x17. in emitPtrauthDiscriminator()
1769 .addReg(AArch64::X17) in emitPtrauthDiscriminator()
1772 .addImm(0)); in emitPtrauthDiscriminator()
1775 .addReg(AArch64::X17) in emitPtrauthDiscriminator()
1776 .addReg(AArch64::X17) in emitPtrauthDiscriminator()
1780 return AArch64::X17; in emitPtrauthDiscriminator()
1784 unsigned InstsEmitted = 0; in emitPtrauthAuthResign()
1793 // mov x17, x0 in emitPtrauthAuthResign()
1794 // movk x17, #disc, lsl #48 in emitPtrauthAuthResign()
1795 // autia x16, x17 in emitPtrauthAuthResign()
1796 // mov x17, x16 in emitPtrauthAuthResign()
1797 // xpaci x17 in emitPtrauthAuthResign()
1798 // cmp x16, x17 in emitPtrauthAuthResign()
1800 // mov x16, x17 in emitPtrauthAuthResign()
1803 // mov x17, x1 in emitPtrauthAuthResign()
1804 // movk x17, #disc, lsl #48 in emitPtrauthAuthResign()
1805 // pacib x16, x17 in emitPtrauthAuthResign()
1810 // mov x17, x0 in emitPtrauthAuthResign()
1811 // movk x17, #disc, lsl #48 in emitPtrauthAuthResign()
1813 // mov x17, x16 in emitPtrauthAuthResign()
1814 // xpaci x17 in emitPtrauthAuthResign()
1815 // cmp x16, x17 in emitPtrauthAuthResign()
1817 // brk #<0xc470 + aut key> in emitPtrauthAuthResign()
1819 // mov x17, x1 in emitPtrauthAuthResign()
1820 // movk x17, #disc, lsl #48 in emitPtrauthAuthResign()
1821 // pacib x16, x17 ; if AUTPAC in emitPtrauthAuthResign()
1861 auto AUTKey = (AArch64PACKey::ID)MI->getOperand(0).getImm(); in emitPtrauthAuthResign()
1867 // Compute aut discriminator into x17 in emitPtrauthAuthResign()
1875 // autia x16, x17 ; if !AUTZero in emitPtrauthAuthResign()
1897 // XPAC has tied src/dst: use x17 as a temporary copy. in emitPtrauthAuthResign()
1898 // mov x17, x16 in emitPtrauthAuthResign()
1900 .addReg(AArch64::X17) in emitPtrauthAuthResign()
1903 .addImm(0)); in emitPtrauthAuthResign()
1906 // xpaci x17 in emitPtrauthAuthResign()
1909 MCInstBuilder(XPACOpc).addReg(AArch64::X17).addReg(AArch64::X17)); in emitPtrauthAuthResign()
1912 // cmp x16, x17 in emitPtrauthAuthResign()
1916 .addReg(AArch64::X17) in emitPtrauthAuthResign()
1917 .addImm(0)); in emitPtrauthAuthResign()
1929 // brk #<0xc470 + aut key> in emitPtrauthAuthResign()
1931 MCInstBuilder(AArch64::BRK).addImm(0xc470 | AUTKey)); in emitPtrauthAuthResign()
1939 // mov x17, x16 in emitPtrauthAuthResign()
1943 .addReg(AArch64::X17) in emitPtrauthAuthResign()
1944 .addImm(0)); in emitPtrauthAuthResign()
1975 // Compute pac discriminator into x17 in emitPtrauthAuthResign()
1983 // pacib x16, x17 ; if !PACZero in emitPtrauthAuthResign()
2000 unsigned InstsEmitted = 0; in emitPtrauthBranch()
2002 unsigned BrTarget = MI->getOperand(0).getReg(); in emitPtrauthBranch()
2013 // Compute discriminator into x17 in emitPtrauthBranch()
2046 APInt Offset(64, 0); in lowerConstantPtrAuth()
2062 if (Offset.sgt(0)) in lowerConstantPtrAuth()
2065 else if (Offset.slt(0)) in lowerConstantPtrAuth()
2074 "' out of range [0, " + in lowerConstantPtrAuth()
2080 "' out of range [0, 0xFFFF]"); in lowerConstantPtrAuth()
2088 unsigned DstReg = MI.getOperand(0).getReg(); in LowerLOADauthptrstatic()
2092 "key is out of range [0, AArch64PACKey::LAST]"); in LowerLOADauthptrstatic()
2096 "constant discriminator is out of range [0, 0xffff]"); in LowerLOADauthptrstatic()
2109 assert(GAOp.getOffset() == 0 && in LowerLOADauthptrstatic()
2120 assert(GAOp.getOffset() == 0 && in LowerLOADauthptrstatic()
2146 unsigned InstsEmitted = 0; in LowerMOVaddrPAC()
2153 MachineOperand GAOp = MI.getOperand(0); in LowerMOVaddrPAC()
2156 "key is out of range [0, AArch64PACKey::LAST]"); in LowerMOVaddrPAC()
2161 "constant discriminator is out of range [0, 0xffff]"); in LowerMOVaddrPAC()
2164 GAOp.setOffset(0); in LowerMOVaddrPAC()
2171 // add offset to x16 if offset != 0 in LowerMOVaddrPAC()
2176 // add offset to x16 if offset != 0 in LowerMOVaddrPAC()
2182 // - offset < 0: in LowerMOVaddrPAC()
2183 // movn+movk sequence filling x17 register with the offset (up to 4 in LowerMOVaddrPAC()
2185 // add x16, x16, x17 in LowerMOVaddrPAC()
2186 // - offset > 0: in LowerMOVaddrPAC()
2187 // movz+movk sequence filling x17 register with the offset (up to 4 in LowerMOVaddrPAC()
2189 // add x16, x16, x17 in LowerMOVaddrPAC()
2192 // - 0 discriminator: in LowerMOVaddrPAC()
2194 // - Non-0 discriminator, no address discriminator: in LowerMOVaddrPAC()
2195 // mov x17, #Disc in LowerMOVaddrPAC()
2196 // pacia x16, x17 in LowerMOVaddrPAC()
2226 .addImm(0)); in LowerMOVaddrPAC()
2229 if (Offset != 0) { in LowerMOVaddrPAC()
2230 const uint64_t AbsOffset = (Offset > 0 ? Offset : -((uint64_t)Offset)); in LowerMOVaddrPAC()
2231 const bool IsNeg = Offset < 0; in LowerMOVaddrPAC()
2233 for (int BitPos = 0; BitPos != 24 && (AbsOffset >> BitPos); in LowerMOVaddrPAC()
2239 .addImm((AbsOffset >> BitPos) & 0xfff) in LowerMOVaddrPAC()
2245 .addReg(AArch64::X17) in LowerMOVaddrPAC()
2246 .addImm((IsNeg ? ~UOffset : UOffset) & 0xffff) in LowerMOVaddrPAC()
2247 .addImm(/*shift=*/0)); in LowerMOVaddrPAC()
2252 return Shifted != 0; in LowerMOVaddrPAC()
2253 for (int I = 0; I != 64 - BitPos; I += 16) in LowerMOVaddrPAC()
2254 if (((Shifted >> I) & 0xffff) != 0xffff) in LowerMOVaddrPAC()
2260 .addReg(AArch64::X17) in LowerMOVaddrPAC()
2261 .addReg(AArch64::X17) in LowerMOVaddrPAC()
2262 .addImm((UOffset >> BitPos) & 0xffff) in LowerMOVaddrPAC()
2268 .addReg(AArch64::X17) in LowerMOVaddrPAC()
2269 .addImm(/*shift=*/0)); in LowerMOVaddrPAC()
2274 if (Disc != 0) { in LowerMOVaddrPAC()
2277 .addReg(AArch64::X17) in LowerMOVaddrPAC()
2280 .addImm(0)); in LowerMOVaddrPAC()
2282 .addReg(AArch64::X17) in LowerMOVaddrPAC()
2283 .addReg(AArch64::X17) in LowerMOVaddrPAC()
2288 .addReg(AArch64::X17) in LowerMOVaddrPAC()
2290 .addImm(/*shift=*/0)); in LowerMOVaddrPAC()
2292 DiscReg = AArch64::X17; in LowerMOVaddrPAC()
2354 // -fpatchable-function-entry=N,0. The entry MBB is guaranteed to be in emitInstruction()
2360 int64_t Imm = MI->getOperand(0).getImm(); in emitInstruction()
2373 Register DestReg = MI->getOperand(0).getReg(); in emitInstruction()
2396 MovK.addOperand(MCOperand::createImm(0)); in emitInstruction()
2401 // It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0". in emitInstruction()
2409 MI->getOperand(1).getImm() == 0) { in emitInstruction()
2412 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in emitInstruction()
2486 Register ScratchReg = MI->getOperand(0).getReg() == AArch64::X16 in emitInstruction()
2487 ? AArch64::X17 in emitInstruction()
2497 .addImm(0)); in emitInstruction()
2507 .addImm(/*shift=*/0)); in emitInstruction()
2518 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in emitInstruction()
2532 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in emitInstruction()
2538 MCInstLowering.lowerOperand(MI->getOperand(0), Dest); in emitInstruction()
2549 TmpInstDSB.addOperand(MCOperand::createImm(0xf)); in emitInstruction()
2553 TmpInstISB.addOperand(MCOperand::createImm(0xf)); in emitInstruction()
2572 const MachineOperand &MO_Sym = MI->getOperand(0); in emitInstruction()
2597 Ldr.addOperand(MCOperand::createImm(0)); in emitInstruction()
2611 Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0))); in emitInstruction()
2692 TS->emitARM64WinCFIAllocStack(MI->getOperand(0).getImm()); in emitInstruction()
2696 TS->emitARM64WinCFISaveFPLR(MI->getOperand(0).getImm()); in emitInstruction()
2700 assert(MI->getOperand(0).getImm() < 0 && in emitInstruction()
2702 TS->emitARM64WinCFISaveFPLRX(-MI->getOperand(0).getImm()); in emitInstruction()
2706 TS->emitARM64WinCFISaveReg(MI->getOperand(0).getImm(), in emitInstruction()
2711 assert(MI->getOperand(1).getImm() < 0 && in emitInstruction()
2713 TS->emitARM64WinCFISaveRegX(MI->getOperand(0).getImm(), in emitInstruction()
2718 if (MI->getOperand(1).getImm() == 30 && MI->getOperand(0).getImm() >= 19 && in emitInstruction()
2719 MI->getOperand(0).getImm() <= 28) { in emitInstruction()
2720 assert((MI->getOperand(0).getImm() - 19) % 2 == 0 && in emitInstruction()
2722 TS->emitARM64WinCFISaveLRPair(MI->getOperand(0).getImm(), in emitInstruction()
2726 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) && in emitInstruction()
2728 TS->emitARM64WinCFISaveRegP(MI->getOperand(0).getImm(), in emitInstruction()
2733 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) && in emitInstruction()
2735 assert(MI->getOperand(2).getImm() < 0 && in emitInstruction()
2737 TS->emitARM64WinCFISaveRegPX(MI->getOperand(0).getImm(), in emitInstruction()
2742 TS->emitARM64WinCFISaveFReg(MI->getOperand(0).getImm(), in emitInstruction()
2747 assert(MI->getOperand(1).getImm() < 0 && in emitInstruction()
2749 TS->emitARM64WinCFISaveFRegX(MI->getOperand(0).getImm(), in emitInstruction()
2754 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) && in emitInstruction()
2756 TS->emitARM64WinCFISaveFRegP(MI->getOperand(0).getImm(), in emitInstruction()
2761 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) && in emitInstruction()
2763 assert(MI->getOperand(2).getImm() < 0 && in emitInstruction()
2765 TS->emitARM64WinCFISaveFRegPX(MI->getOperand(0).getImm(), in emitInstruction()
2774 TS->emitARM64WinCFIAddFP(MI->getOperand(0).getImm()); in emitInstruction()
2798 assert(MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1 && in emitInstruction()
2800 assert(MI->getOperand(2).getImm() >= 0 && in emitInstruction()
2804 TS->emitARM64WinCFISaveAnyRegQP(MI->getOperand(0).getImm(), in emitInstruction()
2809 assert(MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1 && in emitInstruction()
2811 assert(MI->getOperand(2).getImm() < 0 && in emitInstruction()
2815 TS->emitARM64WinCFISaveAnyRegQPX(MI->getOperand(0).getImm(), in emitInstruction()
2858 Ldr.addOperand(MCOperand::createImm(0)); in emitMachOIFuncStubBody()
2865 .addImm(0), in emitMachOIFuncStubBody()
2920 .addImm(0) in emitMachOIFuncStubHelperBody()
2921 .addImm(0), in emitMachOIFuncStubHelperBody()
2924 for (int I = 0; I != 4; ++I) in emitMachOIFuncStubHelperBody()
2933 for (int I = 0; I != 4; ++I) in emitMachOIFuncStubHelperBody()
2971 Ldr.addOperand(MCOperand::createImm(0)); in emitMachOIFuncStubHelperBody()
2978 .addImm(0), in emitMachOIFuncStubHelperBody()
2984 .addImm(0) in emitMachOIFuncStubHelperBody()
2985 .addImm(0), in emitMachOIFuncStubHelperBody()
3023 return MCSymbolRefExpr::create(MCInstLowering.GetGlobalValueSymbol(GV, 0), in lowerConstant()