1 //===--------------------- InstrBuilder.cpp ---------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
24 #define DEBUG_TYPE "llvm-mca-instrbuilder"
61   // This map stores the number of cycles contributed by sub-resources that are  in initializeUsedResources()
72     const MCProcResourceDesc &PR = *SM.getProcResource(PRE->ProcResourceIdx);  in initializeUsedResources()
73     if (!PRE->ReleaseAtCycle) {  in initializeUsedResources()
84     uint64_t Mask = ProcResourceMasks[PRE->ProcResourceIdx];  in initializeUsedResources()
93     CycleSegment RCy(0, PRE->ReleaseAtCycle, false);  in initializeUsedResources()
97       SuperResources[Super] += PRE->ReleaseAtCycle;  in initializeUsedResources()
149         B.second.CS.subtract(A.second.size() - SuperResources[A.first]);  in initializeUsedResources()
169   // On top of those 2cy, SchedWriteRes explicitly specifies an extra latency  in initializeUsedResources()
171   // extra delay on top of the 2 cycles latency.  in initializeUsedResources()
172   // During those extra cycles, HWPort01 is not usable by other instructions.  in initializeUsedResources()
185   // Identify extra buffers that are consumed through super resources.  in initializeUsedResources()
189       if (PR.BufferSize == -1)  in initializeUsedResources()
210       uint64_t Current = BufferIDs & (-BufferIDs);  in initializeUsedResources()
246       --NumExplicitDefs;  in verifyOperands()
256     const MCOperand &Op = MCI.getOperand(MCDesc.getNumOperands() - 1);  in verifyOperands()
280   //     either the last operand of the sequence (excluding extra operands  in populateWrites()
284   // These assumptions work quite well for most out-of-order in-tree targets  in populateWrites()
290   // The algorithm allows non-register operands between register operand  in populateWrites()
292   // implicit operand increment (-mtriple=armv7):  in populateWrites()
312   // non-register operands between register definitions.  The optional  in populateWrites()
313   // definition is still at index #(NumOperands-1).  in populateWrites()
315   // According to assumption 2. register reads start at #(NumExplicitDefs-1).  in populateWrites()
324   unsigned NumVariadicOps = MCI.getNumOperands() - MCDesc.getNumOperands();  in populateWrites()
326   // Iterate over the operands list, and skip non-register or constant register  in populateWrites()
330   unsigned OptionalDefIdx = MCDesc.getNumOperands() - 1;  in populateWrites()
446   unsigned NumExplicitUses = MCDesc.getNumOperands() - MCDesc.getNumDefs();  in populateReads()
450     --NumExplicitUses;  in populateReads()
451   unsigned NumVariadicOps = MCI.getNumOperands() - MCDesc.getNumOperands();  in populateReads()
547   while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())  in getVariantSchedClassID()
573   bool IsVariant = SM.getSchedClassDesc(SchedClassID)->isVariant();  in createInstrDescImpl()
599   ID->NumMicroOps = SCDesc.NumMicroOps;  in createInstrDescImpl()
600   ID->SchedClassID = SchedClassID;  in createInstrDescImpl()
626   LLVM_DEBUG(dbgs() << "\t\tMaxLatency=" << ID->MaxLatency << '\n');  in createInstrDescImpl()
627   LLVM_DEBUG(dbgs() << "\t\tNumMicroOps=" << ID->NumMicroOps << '\n');  in createInstrDescImpl()
635   if ((ID->IsRecyclable = !IsVariadic && !IsVariant)) {  in createInstrDescImpl()
693       NewIS->reset();  in createInstruction()
706   NewIS->setMayLoad(MCDesc.mayLoad());  in createInstruction()
707   NewIS->setMayStore(MCDesc.mayStore());  in createInstruction()
708   NewIS->setHasSideEffects(MCDesc.hasUnmodeledSideEffects());  in createInstruction()
709   NewIS->setBeginGroup(SCDesc.BeginGroup);  in createInstruction()
710   NewIS->setEndGroup(SCDesc.EndGroup);  in createInstruction()
711   NewIS->setRetireOOO(SCDesc.RetireOOO);  in createInstruction()
720     IsZeroIdiom = MCIA->isZeroIdiom(MCI, Mask, ProcID);  in createInstruction()
722         IsZeroIdiom || MCIA->isDependencyBreaking(MCI, Mask, ProcID);  in createInstruction()
723     if (MCIA->isOptimizableRegisterMove(MCI, ProcID))  in createInstruction()
724       NewIS->setOptimizableMove();  in createInstruction()
734       // Skip non-register operands.  in createInstruction()
749     if (IsInstRecycled && Idx < NewIS->getUses().size()) {  in createInstruction()
750       NewIS->getUses()[Idx] = ReadState(RD, RegID);  in createInstruction()
751       RS = &NewIS->getUses()[Idx++];  in createInstruction()
753       NewIS->getUses().emplace_back(RD, RegID);  in createInstruction()
754       RS = &NewIS->getUses().back();  in createInstruction()
763           RS->setIndependentFromDef();  in createInstruction()
773             RS->setIndependentFromDef();  in createInstruction()
778   if (IsInstRecycled && Idx < NewIS->getUses().size())  in createInstruction()
779     NewIS->getUses().pop_back_n(NewIS->getUses().size() - Idx);  in createInstruction()
790   // underlying super-registers using an APInt.  in createInstruction()
794   // register writes implicitly clear the upper portion of a super-register.  in createInstruction()
796     MCIA->clearsSuperRegisters(MRI, MCI, WriteMask);  in createInstruction()
812     if (IsInstRecycled && Idx < NewIS->getDefs().size()) {  in createInstruction()
813       NewIS->getDefs()[Idx++] =  in createInstruction()
818       NewIS->getDefs().emplace_back(WD, RegID,  in createInstruction()
825   if (IsInstRecycled && Idx < NewIS->getDefs().size())  in createInstruction()
826     NewIS->getDefs().pop_back_n(NewIS->getDefs().size() - Idx);  in createInstruction()