27 WriteRef::WriteRef(unsigned SourceIndex, WriteState *WS)  in WriteRef()  argument
29       Write(WS) {}  in WriteRef()
107   for (WriteState &WS : IS->getDefs()) {  in onInstructionExecuted()
108     if (WS.isEliminated())  in onInstructionExecuted()
111     MCPhysReg RegID = WS.getRegisterID();  in onInstructionExecuted()
118     assert(WS.getCyclesLeft() != UNKNOWN_CYCLES &&  in onInstructionExecuted()
120     assert(WS.getCyclesLeft() <= 0 && "Invalid cycles left for this write!");  in onInstructionExecuted()
127     if (WR.getWriteState() == &WS)  in onInstructionExecuted()
132       if (OtherWR.getWriteState() == &WS)  in onInstructionExecuted()
136     if (!WS.clearsSuperRegisters())  in onInstructionExecuted()
141       if (OtherWR.getWriteState() == &WS)  in onInstructionExecuted()
230   WriteState &WS = *Write.getWriteState();  in addRegisterWrite()  local
231   MCPhysReg RegID = WS.getRegisterID();  in addRegisterWrite()
256   bool IsWriteZero = WS.isWriteZero();  in addRegisterWrite()
257   bool IsEliminated = WS.isEliminated();  in addRegisterWrite()
260   WS.setPRF(RRI.IndexPlusCost.first);  in addRegisterWrite()
266     if (!WS.clearsSuperRegisters()) {  in addRegisterWrite()
276         OtherWS->addUser(OtherWrite.getSourceIndex(), &WS);  in addRegisterWrite()
283       WS.clearsSuperRegisters() ? RegID : WS.getRegisterID();  in addRegisterWrite()
296       if (OtherWS->getLatency() > WS.getLatency()) {  in addRegisterWrite()
319   if (!WS.clearsSuperRegisters())  in addRegisterWrite()
333     const WriteState &WS, MutableArrayRef<unsigned> FreedPhysRegs) {  in removeRegisterWrite()  argument
336   if (WS.isEliminated())  in removeRegisterWrite()
339   MCPhysReg RegID = WS.getRegisterID();  in removeRegisterWrite()
346   assert(WS.getCyclesLeft() != UNKNOWN_CYCLES &&  in removeRegisterWrite()
348   assert(WS.getCyclesLeft() <= 0 && "Invalid cycles left for this write!");  in removeRegisterWrite()
350   bool ShouldFreePhysRegs = !WS.isWriteZero();  in removeRegisterWrite()
355     if (!WS.clearsSuperRegisters()) {  in removeRegisterWrite()
365   if (WR.getWriteState() == &WS)  in removeRegisterWrite()
370     if (OtherWR.getWriteState() == &WS)  in removeRegisterWrite()
374   if (!WS.clearsSuperRegisters())  in removeRegisterWrite()
379     if (OtherWR.getWriteState() == &WS)  in removeRegisterWrite()
384 bool RegisterFile::canEliminateMove(const WriteState &WS, const ReadState &RS,  in canEliminateMove()  argument
387   const RegisterMapping &RMTo = RegisterMappings[WS.getRegisterID()];  in canEliminateMove()
418   if (RRITo.RenameAs && RRITo.RenameAs != WS.getRegisterID())  in canEliminateMove()
419     if (!WS.clearsSuperRegisters())  in canEliminateMove()
451     const WriteState &WS = Writes[E - (I + 1)];  in tryEliminateMoveOrSwap()  local
452     if (!canEliminateMove(WS, RS, RegisterFileIndex))  in tryEliminateMoveOrSwap()
458     WriteState &WS = Writes[E - (I + 1)];  in tryEliminateMoveOrSwap()  local
461     const RegisterMapping &RMTo = RegisterMappings[WS.getRegisterID()];  in tryEliminateMoveOrSwap()
468     MCPhysReg AliasReg = RRITo.RenameAs ? RRITo.RenameAs : WS.getRegisterID();  in tryEliminateMoveOrSwap()
479       WS.setWriteZero();  in tryEliminateMoveOrSwap()
483     WS.setEliminated();  in tryEliminateMoveOrSwap()
559       const WriteState &WS = *WR.getWriteState();  in collectWrites()
561              << MRI.getName(WS.getRegisterID()) << " (defined by instruction #"  in collectWrites()
580     const WriteState *WS = WR.getWriteState();  in checkRAWHazards()  local
581     unsigned WriteResID = WS->getWriteResourceID();  in checkRAWHazards()
584     if (WS->getCyclesLeft() == UNKNOWN_CYCLES) {  in checkRAWHazards()
593     int CyclesLeft = WS->getCyclesLeft() - ReadAdvance;  in checkRAWHazards()
642     WriteState &WS = *WR.getWriteState();  in addRegisterRead()  local
644     WS.addUser(WR.getSourceIndex(), &RS, ReadAdvance);  in addRegisterRead()