Lines Matching refs:inst
63 WinEH::Instruction &inst) {
66 b2 = (inst.Operation & 0x0F);
67 switch (static_cast<Win64EH::UnwindOpcodes>(inst.Operation)) {
71 EmitAbsDifference(streamer, inst.Label, begin);
72 b2 |= (inst.Register & 0x0F) << 4;
76 EmitAbsDifference(streamer, inst.Label, begin);
77 if (inst.Offset > 512 * 1024 - 8) {
80 w = inst.Offset & 0xFFF8;
82 w = inst.Offset >> 16;
85 w = inst.Offset >> 3;
90 b2 |= (((inst.Offset - 8) >> 3) & 0x0F) << 4;
91 EmitAbsDifference(streamer, inst.Label, begin);
95 EmitAbsDifference(streamer, inst.Label, begin);
100 b2 |= (inst.Register & 0x0F) << 4;
101 EmitAbsDifference(streamer, inst.Label, begin);
103 w = inst.Offset >> 3;
104 if (inst.Operation == Win64EH::UOP_SaveXMM128)
110 b2 |= (inst.Register & 0x0F) << 4;
111 EmitAbsDifference(streamer, inst.Label, begin);
113 if (inst.Operation == Win64EH::UOP_SaveXMM128Big)
114 w = inst.Offset & 0xFFF0;
116 w = inst.Offset & 0xFFF8;
118 w = inst.Offset >> 16;
122 if (inst.Offset == 1)
124 EmitAbsDifference(streamer, inst.Label, begin);
209 WinEH::Instruction inst = info->Instructions.back();
211 EmitUnwindCode(streamer, info->Begin, inst);
446 const WinEH::Instruction &inst) {
448 switch (static_cast<Win64EH::UnwindOpcodes>(inst.Operation)) {
452 b = (inst.Offset >> 4) & 0x1F;
456 uint16_t hw = (inst.Offset >> 4) & 0x7FF;
468 w = inst.Offset >> 4;
484 b = (inst.Offset >> 3);
493 b |= (inst.Offset >> 3) & 0x1F;
498 b |= ((inst.Offset - 1) >> 3) & 0x3F;
503 b |= (inst.Offset >> 3) & 0x3F;
507 assert(inst.Register >= 19 && "Saved reg must be >= 19");
508 reg = inst.Register - 19;
511 b = ((reg & 0x3) << 6) | (inst.Offset >> 3);
515 assert(inst.Register >= 19 && "Saved reg must be >= 19");
516 reg = inst.Register - 19;
519 b = ((reg & 0x7) << 5) | ((inst.Offset >> 3) - 1);
523 assert(inst.Register >= 19 && "Saved registers must be >= 19");
524 reg = inst.Register - 19;
527 b = ((reg & 0x3) << 6) | (inst.Offset >> 3);
531 assert(inst.Register >= 19 && "Saved registers must be >= 19");
532 reg = inst.Register - 19;
535 b = ((reg & 0x3) << 6) | ((inst.Offset >> 3) - 1);
539 assert(inst.Register >= 19 && "Saved reg must be >= 19");
540 reg = inst.Register - 19;
545 b = ((reg & 0x3) << 6) | (inst.Offset >> 3);
549 assert(inst.Register >= 8 && "Saved dreg must be >= 8");
550 reg = inst.Register - 8;
553 b = ((reg & 0x3) << 6) | (inst.Offset >> 3);
557 assert(inst.Register >= 8 && "Saved dreg must be >= 8");
558 reg = inst.Register - 8;
561 b = ((reg & 0x7) << 5) | ((inst.Offset >> 3) - 1);
565 assert(inst.Register >= 8 && "Saved dregs must be >= 8");
566 reg = inst.Register - 8;
569 b = ((reg & 0x3) << 6) | (inst.Offset >> 3);
573 assert(inst.Register >= 8 && "Saved dregs must be >= 8");
574 reg = inst.Register - 8;
577 b = ((reg & 0x3) << 6) | ((inst.Offset >> 3) - 1);
625 int Op = inst.Operation - Win64EH::UOP_SaveAnyRegI;
629 int Offset = inst.Offset >> 3;
636 assert(inst.Register < 32);
637 b = inst.Register | (Writeback << 5) | (Paired << 6);
1335 for (const WinEH::Instruction &inst : EpilogInstrs)
1336 ARM64EmitUnwindCode(streamer, inst);
1586 static bool isARMTerminator(const WinEH::Instruction &inst) {
1587 switch (static_cast<Win64EH::UnwindOpcodes>(inst.Operation)) {
1600 const WinEH::Instruction &inst) {
1603 switch (static_cast<Win64EH::UnwindOpcodes>(inst.Operation)) {
1607 assert((inst.Offset & 3) == 0);
1608 assert(inst.Offset / 4 <= 0x7f);
1609 streamer.emitInt8(inst.Offset / 4);
1612 assert((inst.Register & ~0x5fff) == 0);
1613 lr = (inst.Register >> 14) & 1;
1614 w = 0x8000 | (inst.Register & 0x1fff) | (lr << 13);
1619 assert(inst.Register <= 0x0f);
1620 streamer.emitInt8(0xc0 | inst.Register);
1623 assert(inst.Register >= 4 && inst.Register <= 7);
1624 assert(inst.Offset <= 1);
1625 streamer.emitInt8(0xd0 | (inst.Register - 4) | (inst.Offset << 2));
1628 assert(inst.Register >= 8 && inst.Register <= 11);
1629 assert(inst.Offset <= 1);
1630 streamer.emitInt8(0xd8 | (inst.Register - 8) | (inst.Offset << 2));
1633 assert(inst.Register >= 8 && inst.Register <= 15);
1634 streamer.emitInt8(0xe0 | (inst.Register - 8));
1637 assert((inst.Offset & 3) == 0);
1638 assert(inst.Offset / 4 <= 0x3ff);
1639 w = 0xe800 | (inst.Offset / 4);
1644 assert((inst.Register & ~0x40ff) == 0);
1645 lr = (inst.Register >> 14) & 1;
1646 w = 0xec00 | (inst.Register & 0x0ff) | (lr << 8);
1651 assert((inst.Offset & 3) == 0);
1652 assert(inst.Offset / 4 <= 0x0f);
1654 streamer.emitInt8(inst.Offset / 4);
1657 assert(inst.Register <= 15);
1658 assert(inst.Offset <= 15);
1659 assert(inst.Register <= inst.Offset);
1661 streamer.emitInt8((inst.Register << 4) | inst.Offset);
1664 assert(inst.Register >= 16 && inst.Register <= 31);
1665 assert(inst.Offset >= 16 && inst.Offset <= 31);
1666 assert(inst.Register <= inst.Offset);
1668 streamer.emitInt8(((inst.Register - 16) << 4) | (inst.Offset - 16));
1671 assert((inst.Offset & 3) == 0);
1672 assert(inst.Offset / 4 <= 0xffff);
1673 w = inst.Offset / 4;
1679 assert((inst.Offset & 3) == 0);
1680 assert(inst.Offset / 4 <= 0xffffff);
1681 w = inst.Offset / 4;
1688 assert((inst.Offset & 3) == 0);
1689 assert(inst.Offset / 4 <= 0xffff);
1690 w = inst.Offset / 4;
1696 assert((inst.Offset & 3) == 0);
1697 assert(inst.Offset / 4 <= 0xffffff);
1698 w = inst.Offset / 4;
1721 if (inst.Offset & (0xffu << (8 * i)))
1724 streamer.emitInt8((inst.Offset >> (8 * i)) & 0xff);
2484 WinEH::Instruction inst = info->Instructions.back();
2486 ARMEmitUnwindCode(streamer, inst);
2492 for (const WinEH::Instruction &inst : EpilogInstrs)
2493 ARMEmitUnwindCode(streamer, inst);