Lines Matching +full:dc +full:- +full:valid
1 //===-- lib/MC/Disassembler.cpp - Disassembler Public C Interface ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 #include "llvm-c/Disassembler.h"
40 // the header llvm-c/Disassembler.h . The pointer to the block and the
55 std::unique_ptr<const MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TT));
62 TheTarget->createMCAsmInfo(*MRI, TT, MCOptions));
66 std::unique_ptr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo());
71 TheTarget->createMCSubtargetInfo(TT, CPU, Features));
83 TheTarget->createMCDisassembler(*STI, *Ctx));
88 TheTarget->createMCRelocationInfo(TT, *Ctx));
92 std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
94 DisAsm->setSymbolizer(std::move(Symbolizer));
97 int AsmPrinterVariant = MAI->getAssemblerDialect();
98 std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
103 LLVMDisasmContext *DC = new LLVMDisasmContext(
107 if (!DC)
110 DC->setCPU(CPU);
111 return DC;
133 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
134 delete DC;
137 /// Emits the comments that are stored in \p DC comment stream.
139 static void emitComments(LLVMDisasmContext *DC,
142 StringRef Comments = DC->CommentsToEmit.str();
144 const MCAsmInfo *MAI = DC->getAsmInfo();
145 StringRef CommentBegin = MAI->getCommentString();
146 unsigned CommentColumn = MAI->getCommentColumn();
162 DC->CommentsToEmit.clear();
166 /// scheduling model, based on \p DC information.
167 /// \return The maximum expected latency over all the operands or -1
169 static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
170 const int NoInformationAvailable = -1;
173 if (DC->getCPU().empty())
177 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
178 InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU());
180 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
192 /// Gets latency information for \p Inst, based on \p DC information.
193 /// \return The maximum expected latency over all the definitions or -1
195 static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
197 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
198 const MCSchedModel SCModel = STI->getSchedModel();
199 const int NoInformationAvailable = -1;
205 return getItineraryLatency(DC, Inst);
208 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
213 if (!SCDesc || !SCDesc->isValid() || SCDesc->isVariant())
218 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
221 const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,
223 Latency = std::max(Latency, WLEntry->Cycles);
229 /// Emits latency information in DC->CommentStream for \p Inst, based
230 /// on the information available in \p DC.
231 static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
232 int Latency = getLatency(DC, Inst);
238 DC->CommentStream << "Latency: " << Latency << '\n';
243 // disassembler context specified in the parameter DC. The bytes of the
246 // the PC parameter. If a valid instruction can be disassembled its string is
249 // instruction or zero if there was no valid instruction. If this function
256 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
262 const MCDisassembler *DisAsm = DC->getDisAsm();
263 MCInstPrinter *IP = DC->getIP();
267 S = DisAsm->getInstruction(Inst, Size, Data, PC, Annotations);
280 IP->printInst(&Inst, PC, AnnotationsStr, *DC->getSubtargetInfo(),
283 if (DC->getOptions() & LLVMDisassembler_Option_PrintLatency)
284 emitLatency(DC, Inst);
286 emitComments(DC, FormattedOS);
289 size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());
305 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
306 MCInstPrinter *IP = DC->getIP();
307 IP->setUseMarkup(true);
308 DC->addOptions(LLVMDisassembler_Option_UseMarkup);
312 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
313 MCInstPrinter *IP = DC->getIP();
314 IP->setPrintImmHex(true);
315 DC->addOptions(LLVMDisassembler_Option_PrintImmHex);
319 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
321 const MCAsmInfo *MAI = DC->getAsmInfo();
322 const MCInstrInfo *MII = DC->getInstrInfo();
323 const MCRegisterInfo *MRI = DC->getRegisterInfo();
324 int AsmPrinterVariant = MAI->getAssemblerDialect();
326 MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter(
327 Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
329 DC->setIP(IP);
330 DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
335 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
336 MCInstPrinter *IP = DC->getIP();
337 IP->setCommentStream(DC->CommentStream);
338 DC->addOptions(LLVMDisassembler_Option_SetInstrComments);
342 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
343 DC->addOptions(LLVMDisassembler_Option_PrintLatency);