Lines Matching +full:0 +full:xfff
4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
32 INTERNAL_REL_ARM64_LONG_BRANCH26 = 0x111,
40 orig &= ~(0xFFF << 10);
41 write32le(T, orig | ((imm & (0xFFF >> rangeLimit)) << 10));
47 // 0x04000000 indicates SIMD/FP registers
48 // 0x00800000 indicates 128 bit
49 if ((orig & 0x04800000) == 0x04800000)
51 if ((imm & ((1 << size) - 1)) != 0)
52 assert(0 && "misaligned ldr/str offset");
58 uint32_t ImmLo = (Imm & 0x3) << 29;
59 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
60 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
81 // is false, or they may be sections that contain 0 bytes. If the
82 // section isn't loaded, the load address will be 0, and it should not
84 if (Section.getLoadAddress() != 0)
94 ImageBase(0) {}
135 Addend = 0;
169 uint64_t Addend = 0;
201 Addend = (orig & 0x03FFFFFF) << 2;
210 Addend = (orig & 0x00FFFFE0) >> 3;
215 Addend = (orig & 0x000FFFE0) >> 3;
221 Addend = ((orig >> 29) & 0x3) | ((orig >> 3) & 0x1FFFFC);
227 Addend = ((orig >> 10) & 0xFFF);
278 write32AArch64Addr(Target, Value, FinalAddress, 0);
285 write32AArch64Imm(Target, Value & 0xFFF, 0);
292 write32AArch64Ldr(Target, Value & 0xFFF);
309 or32le(Target + 12, ((Value + RE.Addend) & 0xFFFF) << 5);
310 or32le(Target + 8, ((Value + RE.Addend) & 0xFFFF0000) >> 11);
311 or32le(Target + 4, ((Value + RE.Addend) & 0xFFFF00000000) >> 27);
312 or32le(Target + 0, ((Value + RE.Addend) & 0xFFFF000000000000) >> 43);
320 write32le(Target, (read32le(Target) & ~(0x03FFFFFF)) |
321 (PCRelVal & 0x0FFFFFFC) >> 2);
329 write32le(Target, (read32le(Target) & ~(0x00FFFFE0)) |
330 (PCRelVal & 0x001FFFFC) << 3);
338 write32le(Target, (read32le(Target) & ~(0x000FFFE0)) |
339 (PCRelVal & 0x0000FFFC) << 3);