Lines Matching full:hi
54 int64_t decodeImmBT4BlT1BlxT2(uint32_t Hi, uint32_t Lo) {
55 uint32_t Imm11H = Hi & 0x07ff;
79 int64_t decodeImmBT4BlT1BlxT2_J1J2(uint32_t Hi, uint32_t Lo) {
80 uint32_t S = Hi & 0x0400;
81 uint32_t I1 = ~((Lo ^ (Hi << 3)) << 10) & 0x00800000;
82 uint32_t I2 = ~((Lo ^ (Hi << 1)) << 11) & 0x00400000;
83 uint32_t Imm10 = Hi & 0x03ff;
124 uint16_t decodeImmMovtT1MovwT3(uint32_t Hi, uint32_t Lo) {
125 uint32_t Imm4 = Hi & 0x0f;
126 uint32_t Imm1 = (Hi >> 10) & 0x01;
147 int64_t decodeRegMovtT1MovwT3(uint32_t Hi, uint32_t Lo) {
197 /// An instruction at address A encodes bytes A+1, A in the first halfword (Hi),
202 : Hi{*reinterpret_cast<support::ulittle16_t *>(FixupPtr)},
205 support::ulittle16_t &Hi; // First halfword
212 : Hi{*reinterpret_cast<const support::ulittle16_t *>(FixupPtr)},
217 : Hi{Writable.Hi}, Lo(Writable.Lo) {}
219 const support::ulittle16_t &Hi; // First halfword
243 static_cast<uint16_t>(R.Hi), static_cast<uint16_t>(R.Lo),
266 static bool checkOpcodeThumb(uint16_t Hi, uint16_t Lo) {
267 return (Hi & FixupInfo<K>::OpcodeMask.Hi) == FixupInfo<K>::Opcode.Hi &&
335 if (!Info.checkOpcode(R.Hi, R.Lo))
347 uint16_t Hi = R.Hi & FixupInfo<Kind>::RegMask.Hi;
349 return Hi == Reg.Hi && Lo == Reg.Lo;
361 assert((Mask.Hi & Reg.Hi) == Reg.Hi && (Mask.Lo & Reg.Lo) == Reg.Lo &&
363 R.Hi = (R.Hi & ~Mask.Hi) | Reg.Hi;
377 assert((Mask.Hi & Imm.Hi) == Imm.Hi && (Mask.Lo & Imm.Lo) == Imm.Lo &&
379 R.Hi = (R.Hi & ~Mask.Hi) | Imm.Hi;
444 ? decodeImmBT4BlT1BlxT2_J1J2(R.Hi, R.Lo)
445 : decodeImmBT4BlT1BlxT2(R.Hi, R.Lo);
450 return SignExtend64<16>(decodeImmMovtT1MovwT3(R.Hi, R.Lo));
455 return SignExtend64<16>(decodeImmMovtT1MovwT3(R.Hi, R.Lo));