Lines Matching refs:Register
115 DenseMap<Register, Register> SrcRegMap;
120 DenseMap<Register, Register> DstRegMap;
122 MachineInstr *getSingleDef(Register Reg, MachineBasicBlock *BB) const;
124 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);
126 bool noUseAfterLastDef(Register Reg, unsigned Dist, unsigned &LastDef);
128 bool isCopyToReg(MachineInstr &MI, Register &SrcReg, Register &DstReg,
132 bool isPlainlyKilled(const MachineInstr *MI, Register Reg) const;
135 bool isKilled(MachineInstr &MI, Register Reg, bool allowFalsePositives) const;
137 MachineInstr *findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB,
138 bool &IsCopy, Register &DstReg,
141 bool regsAreCompatible(Register RegA, Register RegB) const;
144 DenseMap<Register, Register> &RegMap) const;
148 bool regOverlapsSet(const SmallVectorImpl<Register> &Set, Register Reg) const;
150 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
156 bool isProfitableToConv3Addr(Register RegA, Register RegB);
159 MachineBasicBlock::iterator &nmi, Register RegA,
160 Register RegB, unsigned &Dist);
162 bool isDefTooClose(Register Reg, unsigned Dist, MachineInstr *MI);
165 MachineBasicBlock::iterator &nmi, Register Reg);
167 MachineBasicBlock::iterator &nmi, Register Reg);
179 void scanUses(Register DstReg);
184 using TiedOperandMap = SmallDenseMap<Register, TiedPairList>;
298 TwoAddressInstructionImpl::getSingleDef(Register Reg, in getSingleDef()
319 bool TwoAddressInstructionImpl::isRevCopyChain(Register FromReg, Register ToReg, in isRevCopyChain()
321 Register TmpReg = FromReg; in isRevCopyChain()
339 bool TwoAddressInstructionImpl::noUseAfterLastDef(Register Reg, unsigned Dist, in noUseAfterLastDef()
362 bool TwoAddressInstructionImpl::isCopyToReg(MachineInstr &MI, Register &SrcReg, in isCopyToReg()
363 Register &DstReg, bool &IsSrcPhys, in isCopyToReg()
397 Register Reg) const { in isPlainlyKilled()
442 bool TwoAddressInstructionImpl::isKilled(MachineInstr &MI, Register Reg, in isKilled()
460 Register SrcReg, DstReg; in isKilled()
471 static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg) { in isTwoAddrUse()
488 Register Reg, MachineBasicBlock *MBB, bool &IsCopy, Register &DstReg, in findOnlyInterestingUse()
505 Register SrcReg; in findOnlyInterestingUse()
533 static MCRegister getMappedReg(Register Reg, in getMappedReg()
534 DenseMap<Register, Register> &RegMap) { in getMappedReg() argument
536 DenseMap<Register, Register>::iterator SI = RegMap.find(Reg); in getMappedReg()
547 bool TwoAddressInstructionImpl::regsAreCompatible(Register RegA, in regsAreCompatible()
548 Register RegB) const { in regsAreCompatible()
558 const MachineOperand &MO, DenseMap<Register, Register> &RegMap) const { in removeMapRegEntry() argument
563 SmallVector<Register, 2> Srcs; in removeMapRegEntry()
565 Register ToReg = SI.second; in removeMapRegEntry()
570 Register Reg = MO.getReg(); in removeMapRegEntry()
601 Register Dst = MI->getOperand(0).getReg(); in removeClobberedSrcRegMap()
605 Register Src = MI->getOperand(1).getReg(); in removeClobberedSrcRegMap()
617 Register Reg = MO.getReg(); in removeClobberedSrcRegMap()
626 const SmallVectorImpl<Register> &Set, Register Reg) const { in regOverlapsSet()
627 for (Register R : Set) in regOverlapsSet()
636 bool TwoAddressInstructionImpl::isProfitableToCommute(Register RegA, in isProfitableToCommute()
637 Register RegB, in isProfitableToCommute()
638 Register RegC, in isProfitableToCommute()
746 Register RegC = MI->getOperand(RegCIdx).getReg(); in commuteInstruction()
763 Register RegA = MI->getOperand(DstIdx).getReg(); in commuteInstruction()
772 bool TwoAddressInstructionImpl::isProfitableToConv3Addr(Register RegA, in isProfitableToConv3Addr()
773 Register RegB) { in isProfitableToConv3Addr()
791 Register RegA, Register RegB, unsigned &Dist) { in convertInstTo3Addr()
831 void TwoAddressInstructionImpl::scanUses(Register DstReg) { in scanUses()
832 SmallVector<Register, 4> VirtRegPairs; in scanUses()
835 Register NewReg; in scanUses()
836 Register Reg = DstReg; in scanUses()
857 Register ToReg = VirtRegPairs.pop_back_val(); in scanUses()
859 Register FromReg = VirtRegPairs.pop_back_val(); in scanUses()
888 Register SrcReg, DstReg; in processCopy()
911 Register Reg) { in rescheduleMIBelowKill()
948 Register DstReg; in rescheduleMIBelowKill()
960 SmallVector<Register, 2> Uses; in rescheduleMIBelowKill()
961 SmallVector<Register, 2> Kills; in rescheduleMIBelowKill()
962 SmallVector<Register, 2> Defs; in rescheduleMIBelowKill()
966 Register MOReg = MO.getReg(); in rescheduleMIBelowKill()
1009 Register MOReg = MO.getReg(); in rescheduleMIBelowKill()
1076 bool TwoAddressInstructionImpl::isDefTooClose(Register Reg, unsigned Dist, in isDefTooClose()
1099 Register Reg) { in rescheduleKillAboveMI()
1131 Register DstReg; in rescheduleKillAboveMI()
1139 SmallVector<Register, 2> Uses; in rescheduleKillAboveMI()
1140 SmallVector<Register, 2> Kills; in rescheduleKillAboveMI()
1141 SmallVector<Register, 2> Defs; in rescheduleKillAboveMI()
1142 SmallVector<Register, 2> LiveDefs; in rescheduleKillAboveMI()
1146 Register MOReg = MO.getReg(); in rescheduleKillAboveMI()
1179 SmallVector<Register, 2> OtherDefs; in rescheduleKillAboveMI()
1183 Register MOReg = MO.getReg(); in rescheduleKillAboveMI()
1202 for (Register MOReg : OtherDefs) { in rescheduleKillAboveMI()
1258 Register DstOpReg = MI->getOperand(DstOpIdx).getReg(); in tryInstructionCommute()
1259 Register BaseOpReg = MI->getOperand(BaseOpIdx).getReg(); in tryInstructionCommute()
1271 Register OtherOpReg = MI->getOperand(OtherOpIdx).getReg(); in tryInstructionCommute()
1321 Register regA = MI.getOperand(DstIdx).getReg(); in tryInstructionTransform()
1322 Register regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1407 Register Reg = MRI->createVirtualRegister(RC); in tryInstructionTransform()
1474 SmallVector<Register, 4> OrigRegs; in tryInstructionTransform()
1528 Register SrcReg = SrcMO.getReg(); in collectTiedOperands()
1529 Register DstReg = DstMO.getReg(); in collectTiedOperands()
1564 Register LastCopiedReg; in processTiedPairs()
1566 Register RegB = 0; in processTiedPairs()
1573 Register RegA = DstMO.getReg(); in processTiedPairs()
1748 Register RegB = TO.first; in processStatepoint()
1758 Register RegA = DstMO.getReg(); in processStatepoint()
1889 Register SrcReg = mi->getOperand(SrcIdx).getReg(); in run()
1890 Register DstReg = mi->getOperand(DstIdx).getReg(); in run()
1932 Register Reg = mi->getOperand(0).getReg(); in run()
1987 Register DstReg = MI.getOperand(0).getReg(); in eliminateRegSequence()
1989 SmallVector<Register, 4> OrigRegs; in eliminateRegSequence()
2006 Register SrcReg = UseMO.getReg(); in eliminateRegSequence()