141   bool regsAreCompatible(Register RegA, Register RegB) const;
150   bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
156   bool isProfitableToConv3Addr(Register RegA, Register RegB);
160                           Register RegB, unsigned &Dist);
545                                                   Register RegB) const {  in regsAreCompatible()
546   if (RegA == RegB)  in regsAreCompatible()
548   if (!RegA || !RegB)  in regsAreCompatible()
550   return TRI->regsOverlap(RegA, RegB);  in regsAreCompatible()
634                                                       Register RegB,  in isProfitableToCommute()  argument
674     MCRegister FromRegB = getMappedReg(RegB, SrcRegMap);  in isProfitableToCommute()
702   if (!noUseAfterLastDef(RegB, Dist, LastDefB))  in isProfitableToCommute()
723   if (isRevCopyChain(RegB, RegA, MaxDataFlowEdge))  in isProfitableToCommute()
770                                                         Register RegB) {  in isProfitableToConv3Addr()  argument
777   MCRegister FromRegB = getMappedReg(RegB, SrcRegMap);  in isProfitableToConv3Addr()
788     Register RegA, Register RegB, unsigned &Dist) {  in convertInstTo3Addr()  argument
822   DstRegMap.erase(RegB);  in convertInstTo3Addr()
1564   Register RegB = 0;  in processTiedPairs()  local
1575     RegB = MI->getOperand(SrcIdx).getReg();  in processTiedPairs()
1578     if (RegA == RegB) {  in processTiedPairs()
1587     assert(RegB.isVirtual() && "cannot make instruction into two-address form");  in processTiedPairs()
1604     MIB.addReg(RegB, 0, SubRegB);  in processTiedPairs()
1605     const TargetRegisterClass *RC = MRI->getRegClass(RegB);  in processTiedPairs()
1614         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))  in processTiedPairs()
1652     assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&  in processTiedPairs()
1660     if (RegA.isVirtual() && RegB.isVirtual())  in processTiedPairs()
1673       if (MO.getReg() == RegB) {  in processTiedPairs()
1689         LV->getVarInfo(RegB).removeKill(*MI)) {  in processTiedPairs()
1692       LV->addVirtualRegisterKilled(RegB, *PrevMI);  in processTiedPairs()
1696       SrcRegMap[LastCopiedReg] = RegB;  in processTiedPairs()
1713       LiveInterval &LI = LIS->getInterval(RegB);  in processTiedPairs()
1726       if (MO.getReg() == RegB) {  in processTiedPairs()
1746     Register RegB = TO.first;  in processStatepoint()  local
1758     assert(RegB == MI->getOperand(SrcIdx).getReg());  in processStatepoint()
1760     if (RegA == RegB)  in processStatepoint()
1769       const auto &UseLI = LIS->getInterval(RegB);  in processStatepoint()
1772         LLVM_DEBUG(dbgs() << "LIS: " << printReg(RegB, TRI, 0)  in processStatepoint()
1777     } else if (LV && LV->getVarInfo(RegB).findKill(MI->getParent()) != MI) {  in processStatepoint()
1781       LLVM_DEBUG(dbgs() << "LV: " << printReg(RegB, TRI, 0)  in processStatepoint()
1787     if (!MRI->constrainRegClass(RegB, MRI->getRegClass(RegA))) {  in processStatepoint()
1788       LLVM_DEBUG(dbgs() << "MRI: couldn't constrain" << printReg(RegB, TRI, 0)  in processStatepoint()
1794     MRI->replaceRegWith(RegA, RegB);  in processStatepoint()
1798       LiveInterval &LI = LIS->getInterval(RegB);  in processStatepoint()
1815         LV->removeVirtualRegisterKilled(RegB, *MI);  in processStatepoint()
1816       LiveVariables::VarInfo &SrcInfo = LV->getVarInfo(RegB);  in processStatepoint()
1821         LV->addVirtualRegisterKilled(RegB, *KillMI, false);  in processStatepoint()