Lines Matching +full:de +full:- +full:asserts
1 //===- TwoAddressInstructionPass.cpp - Two-Address instruction pass -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // by most register allocators. Two-Address instructions are rewritten
21 // has to be capable of handling the non-SSA nature of these rewritten
27 //===----------------------------------------------------------------------===//
70 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
73 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
74 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
75 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
79 EnableRescheduling("twoaddr-reschedule",
86 "dataflow-edge-limit", cl::Hidden, cl::init(3),
261 "Two-Address instruction pass", false, false)
264 "Two-Address instruction pass", false, false) in INITIALIZE_PASS_DEPENDENCY()
286 auto *LVWrapper = P->getAnalysisIfAvailable<LiveVariablesWrapperPass>(); in TwoAddressInstructionImpl()
287 LV = LVWrapper ? &LVWrapper->getLV() : nullptr; in TwoAddressInstructionImpl()
288 auto *LISWrapper = P->getAnalysisIfAvailable<LiveIntervalsWrapperPass>(); in TwoAddressInstructionImpl()
289 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr; in TwoAddressInstructionImpl()
290 if (auto *AAPass = P->getAnalysisIfAvailable<AAResultsWrapperPass>()) in TwoAddressInstructionImpl()
291 AA = &AAPass->getAAResults(); in TwoAddressInstructionImpl()
301 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { in getSingleDef()
324 if (!Def || !Def->isCopy()) in isRevCopyChain()
327 TmpReg = Def->getOperand(1).getReg(); in isRevCopyChain()
336 /// in the MBB that defines the specified register and the two-address
343 for (MachineOperand &MO : MRI->reg_operands(Reg)) { in noUseAfterLastDef()
345 if (MI->getParent() != MBB || MI->isDebugValue()) in noUseAfterLastDef()
350 if (MO.isUse() && DI->second < LastUse) in noUseAfterLastDef()
351 LastUse = DI->second; in noUseAfterLastDef()
352 if (MO.isDef() && DI->second > LastDef) in noUseAfterLastDef()
353 LastDef = DI->second; in noUseAfterLastDef()
388 SlotIndex useIdx = LIS->getInstructionIndex(*MI); in isPlainlyKilled()
390 assert(I != LR.end() && "Reg must be live-in to use."); in isPlainlyKilled()
391 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx); in isPlainlyKilled()
404 if (LIS && !LIS->isNotInMIMap(*MI)) { in isPlainlyKilled()
406 return isPlainlyKilled(MI, LIS->getInterval(Reg)); in isPlainlyKilled()
408 if (MRI->isReserved(Reg)) in isPlainlyKilled()
410 return all_of(TRI->regunits(Reg), [&](MCRegUnit U) { in isPlainlyKilled()
411 return isPlainlyKilled(MI, LIS->getRegUnit(U)); in isPlainlyKilled()
415 return MI->killsRegister(Reg, /*TRI=*/nullptr); in isPlainlyKilled()
437 /// normal heuristics commute the (two-address) add, which lets
447 if (Reg.isPhysical() && (allowFalsePositives || MRI->hasOneUse(Reg))) in isKilled()
453 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg); in isKilled()
456 if (std::next(Begin) != MRI->def_end()) in isKilled()
458 DefMI = Begin->getParent(); in isKilled()
469 /// Return true if the specified MI uses the specified register as a two-address
486 /// last use instruction if it's a copy or a two-address use.
491 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { in findOnlyInterestingUse()
493 if (MI->getParent() != MBB) in findOnlyInterestingUse()
500 MachineInstr &UseMI = *UseOp->getParent(); in findOnlyInterestingUse()
515 unsigned Src2 = UseOp->getOperandNo(); in findOnlyInterestingUse()
516 if (TII->findCommutedOpIndices(UseMI, Src1, Src2)) { in findOnlyInterestingUse()
536 Reg = SI->second; in getMappedReg()
550 return TRI->regsOverlap(RegA, RegB); in regsAreCompatible()
568 if (TRI->regsOverlap(ToReg, Reg)) in removeMapRegEntry()
582 /// MUL64r %3:gr64, implicit-def $rax, implicit-def $rdx
587 if (MI->isCopy()) { in removeClobberedSrcRegMap()
598 Register Dst = MI->getOperand(0).getReg(); in removeClobberedSrcRegMap()
602 Register Src = MI->getOperand(1).getReg(); in removeClobberedSrcRegMap()
607 for (const MachineOperand &MO : MI->operands()) { in removeClobberedSrcRegMap()
625 if (TRI->regsOverlap(R, Reg)) in regOverlapsSet()
631 /// Return true if it's potentially profitable to commute the two-address
643 // the two-address register. in isProfitableToCommute()
680 // -RegB is not tied to a register and RegC is compatible with RegA. in isProfitableToCommute()
681 // -RegB is tied to the wrong physical register, but RegC is. in isProfitableToCommute()
682 // -RegB is tied to the wrong physical register, and RegC isn't tied. in isProfitableToCommute()
686 // -RegC is not tied to a register and RegB is compatible with RegA. in isProfitableToCommute()
687 // -RegC is tied to the wrong physical register, but RegB is. in isProfitableToCommute()
688 // -RegC is tied to the wrong physical register, and RegB isn't tied. in isProfitableToCommute()
728 if (TII->hasCommutePreference(*MI, Commute)) in isProfitableToCommute()
736 /// Commute a two-address instruction and update the basic block, distance map,
743 Register RegC = MI->getOperand(RegCIdx).getReg(); in commuteInstruction()
745 MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx); in commuteInstruction()
760 Register RegA = MI->getOperand(DstIdx).getReg(); in commuteInstruction()
767 /// Return true if it is profitable to convert the given 2-address instruction
768 /// to a 3-address one.
776 // Turn ADD into a 3-address instruction to avoid a copy. in isProfitableToConv3Addr()
784 /// Convert the specified two-address instruction into a three address one.
790 MachineInstr *NewMI = TII->convertToThreeAddress(*mi, LV, LIS); in convertInstTo3Addr()
794 LLVM_DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi); in convertInstTo3Addr()
795 LLVM_DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI); in convertInstTo3Addr()
798 if (auto OldInstrNum = mi->peekDebugInstrNum()) { in convertInstTo3Addr()
799 assert(mi->getNumExplicitDefs() == 1); in convertInstTo3Addr()
800 assert(NewMI->getNumExplicitDefs() == 1); in convertInstTo3Addr()
803 unsigned OldIdx = mi->defs().begin()->getOperandNo(); in convertInstTo3Addr()
804 unsigned NewIdx = NewMI->defs().begin()->getOperandNo(); in convertInstTo3Addr()
807 unsigned NewInstrNum = NewMI->getDebugInstrNum(); in convertInstTo3Addr()
808 MF->makeDebugValueSubstitution(std::make_pair(OldInstrNum, OldIdx), in convertInstTo3Addr()
812 MBB->erase(mi); // Nuke the old inst. in convertInstTo3Addr()
816 Dist--; in convertInstTo3Addr()
827 /// a two-address instruction.
872 /// point-to maps used to determine future optimizations. e.g.
877 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
923 LiveInterval &LI = LIS->getInterval(Reg); in rescheduleMIBelowKill()
927 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot(); in rescheduleMIBelowKill()
929 if (I != LI.end() && I->start < MBBEndIdx) in rescheduleMIBelowKill()
932 --I; in rescheduleMIBelowKill()
933 KillMI = LIS->getInstructionFromIndex(I->end); in rescheduleMIBelowKill()
935 KillMI = LV->getVarInfo(Reg).findKill(MBB); in rescheduleMIBelowKill()
937 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike()) in rescheduleMIBelowKill()
941 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() || in rescheduleMIBelowKill()
942 KillMI->isBranch() || KillMI->isTerminator()) in rescheduleMIBelowKill()
951 if (!MI->isSafeToMove(AA, SeenStore)) in rescheduleMIBelowKill()
954 if (TII->getInstrLatency(InstrItins, *MI) > 1) in rescheduleMIBelowKill()
961 for (const MachineOperand &MO : MI->operands()) { in rescheduleMIBelowKill()
980 while (End != MBB->end()) { in rescheduleMIBelowKill()
981 End = skipDebugInstructionsForward(End, MBB->end()); in rescheduleMIBelowKill()
982 if (End->isCopy() && regOverlapsSet(Defs, End->getOperand(1).getReg())) in rescheduleMIBelowKill()
983 Defs.push_back(End->getOperand(0).getReg()); in rescheduleMIBelowKill()
1038 while (Begin != MBB->begin() && std::prev(Begin)->isDebugInstr()) in rescheduleMIBelowKill()
1039 --Begin; in rescheduleMIBelowKill()
1045 // first so that the MBB is still well-formed when calling handleMove(). in rescheduleMIBelowKill()
1048 MBB->splice(InsertPos, MBB, CopyMI); in rescheduleMIBelowKill()
1049 if (!CopyMI->isDebugOrPseudoInstr()) in rescheduleMIBelowKill()
1050 LIS->handleMove(*CopyMI); in rescheduleMIBelowKill()
1057 MBB->splice(InsertPos, MBB, Begin, End); in rescheduleMIBelowKill()
1062 LIS->handleMove(*MI); in rescheduleMIBelowKill()
1064 LV->removeVirtualRegisterKilled(Reg, *KillMI); in rescheduleMIBelowKill()
1065 LV->addVirtualRegisterKilled(Reg, *MI); in rescheduleMIBelowKill()
1072 /// Return true if the re-scheduling will put the given instruction too close
1076 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { in isDefTooClose()
1084 unsigned DefDist = DDI->second; in isDefTooClose()
1086 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist)) in isDefTooClose()
1093 /// consider moving the kill instruction above the current two-address
1111 LiveInterval &LI = LIS->getInterval(Reg); in rescheduleKillAboveMI()
1115 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot(); in rescheduleKillAboveMI()
1117 if (I != LI.end() && I->start < MBBEndIdx) in rescheduleKillAboveMI()
1120 --I; in rescheduleKillAboveMI()
1121 KillMI = LIS->getInstructionFromIndex(I->end); in rescheduleKillAboveMI()
1123 KillMI = LV->getVarInfo(Reg).findKill(MBB); in rescheduleKillAboveMI()
1125 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike()) in rescheduleKillAboveMI()
1134 if (!KillMI->isSafeToMove(AA, SeenStore)) in rescheduleKillAboveMI()
1141 for (const MachineOperand &MO : KillMI->operands()) { in rescheduleKillAboveMI()
1148 if (isDefTooClose(MOReg, DI->second, MI)) in rescheduleKillAboveMI()
1212 while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugInstr()) in rescheduleKillAboveMI()
1213 --InsertPos; in rescheduleKillAboveMI()
1216 while (std::prev(From)->isDebugInstr()) in rescheduleKillAboveMI()
1217 --From; in rescheduleKillAboveMI()
1218 MBB->splice(InsertPos, MBB, From, To); in rescheduleKillAboveMI()
1225 LIS->handleMove(*KillMI); in rescheduleKillAboveMI()
1227 LV->removeVirtualRegisterKilled(Reg, *KillMI); in rescheduleKillAboveMI()
1228 LV->addVirtualRegisterKilled(Reg, *MI); in rescheduleKillAboveMI()
1252 if (!MI->isCommutable()) in tryInstructionCommute()
1256 Register DstOpReg = MI->getOperand(DstOpIdx).getReg(); in tryInstructionCommute()
1257 Register BaseOpReg = MI->getOperand(BaseOpIdx).getReg(); in tryInstructionCommute()
1258 unsigned OpsNum = MI->getDesc().getNumOperands(); in tryInstructionCommute()
1259 unsigned OtherOpIdx = MI->getDesc().getNumDefs(); in tryInstructionCommute()
1265 if (OtherOpIdx == BaseOpIdx || !MI->getOperand(OtherOpIdx).isReg() || in tryInstructionCommute()
1266 !TII->findCommutedOpIndices(*MI, BaseOpIdx, OtherOpIdx)) in tryInstructionCommute()
1269 Register OtherOpReg = MI->getOperand(OtherOpIdx).getReg(); in tryInstructionCommute()
1299 OpsNum = MI->getDesc().getNumOperands(); in tryInstructionCommute()
1322 assert(regB.isVirtual() && "cannot make instruction into two-address form"); in tryInstructionTransform()
1345 // re-schedule this MI below it. in tryInstructionTransform()
1351 // If we commuted, regB may have changed so we should re-sample it to avoid in tryInstructionTransform()
1360 // three-address instruction. Check if it is profitable. in tryInstructionTransform()
1375 // re-schedule it before this MI if it's legal. in tryInstructionTransform()
1393 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), in tryInstructionTransform()
1398 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc); in tryInstructionTransform()
1403 TRI->getAllocatableClass( in tryInstructionTransform()
1404 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF)); in tryInstructionTransform()
1405 Register Reg = MRI->createVirtualRegister(RC); in tryInstructionTransform()
1407 if (!TII->unfoldMemoryOperand(*MF, MI, Reg, in tryInstructionTransform()
1416 NewMIs[1]->addRegisterKilled(Reg, TRI); in tryInstructionTransform()
1420 MBB->insert(mi, NewMIs[0]); in tryInstructionTransform()
1421 MBB->insert(mi, NewMIs[1]); in tryInstructionTransform()
1430 NewMIs[1]->findRegisterDefOperandIdx(regA, /*TRI=*/nullptr); in tryInstructionTransform()
1432 NewMIs[1]->findRegisterUseOperandIdx(regB, /*TRI=*/nullptr); in tryInstructionTransform()
1439 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) { in tryInstructionTransform()
1447 if (NewMIs[0]->killsRegister(MO.getReg(), /*TRI=*/nullptr)) in tryInstructionTransform()
1448 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]); in tryInstructionTransform()
1450 assert(NewMIs[1]->killsRegister(MO.getReg(), in tryInstructionTransform()
1453 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]); in tryInstructionTransform()
1456 } else if (LV->removeVirtualRegisterDead(MO.getReg(), MI)) { in tryInstructionTransform()
1457 if (NewMIs[1]->registerDefIsDead(MO.getReg(), in tryInstructionTransform()
1459 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]); in tryInstructionTransform()
1461 assert(NewMIs[0]->registerDefIsDead(MO.getReg(), in tryInstructionTransform()
1464 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]); in tryInstructionTransform()
1469 LV->addVirtualRegisterKilled(Reg, *NewMIs[1]); in tryInstructionTransform()
1479 LIS->RemoveMachineInstrFromMaps(MI); in tryInstructionTransform()
1489 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs); in tryInstructionTransform()
1498 NewMIs[0]->eraseFromParent(); in tryInstructionTransform()
1499 NewMIs[1]->eraseFromParent(); in tryInstructionTransform()
1502 Dist--; in tryInstructionTransform()
1517 unsigned NumOps = MI->getNumOperands(); in collectTiedOperands()
1521 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1524 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands()
1525 MachineOperand &DstMO = MI->getOperand(DstIdx); in collectTiedOperands()
1534 // Deal with undef uses immediately - simply rewrite the src operand. in collectTiedOperands()
1538 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in collectTiedOperands()
1539 MRI->constrainRegClass(DstReg, RC); in collectTiedOperands()
1557 return MI->getOperand(TP.second).isEarlyClobber(); in processTiedPairs()
1570 const MachineOperand &DstMO = MI->getOperand(DstIdx); in processTiedPairs()
1575 RegB = MI->getOperand(SrcIdx).getReg(); in processTiedPairs()
1576 SubRegB = MI->getOperand(SrcIdx).getSubReg(); in processTiedPairs()
1587 assert(RegB.isVirtual() && "cannot make instruction into two-address form"); in processTiedPairs()
1593 for (unsigned i = 0; i != MI->getNumOperands(); ++i) in processTiedPairs()
1595 !MI->getOperand(i).isReg() || in processTiedPairs()
1596 MI->getOperand(i).getReg() != RegA); in processTiedPairs()
1600 MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in processTiedPairs()
1601 TII->get(TargetOpcode::COPY), RegA); in processTiedPairs()
1605 const TargetRegisterClass *RC = MRI->getRegClass(RegB); in processTiedPairs()
1608 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA), in processTiedPairs()
1614 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB)) in processTiedPairs()
1621 --PrevMI; in processTiedPairs()
1626 LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot(); in processTiedPairs()
1629 LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber); in processTiedPairs()
1631 LiveInterval &LI = LIS->getInterval(RegA); in processTiedPairs()
1632 VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator()); in processTiedPairs()
1635 VNI = S.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator()); in processTiedPairs()
1639 for (MCRegUnit Unit : TRI->regunits(RegA)) { in processTiedPairs()
1640 if (LiveRange *LR = LIS->getCachedRegUnit(Unit)) { in processTiedPairs()
1642 LR->getNextValue(LastCopyIdx, LIS->getVNInfoAllocator()); in processTiedPairs()
1643 LR->addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI)); in processTiedPairs()
1651 MachineOperand &MO = MI->getOperand(SrcIdx); in processTiedPairs()
1653 "inconsistent operand info for 2-reg pass"); in processTiedPairs()
1661 MRI->constrainRegClass(RegA, RC); in processTiedPairs()
1663 // The getMatchingSuper asserts guarantee that the register class projected in processTiedPairs()
1671 // Replace other (un-tied) uses of regB with LastCopiedReg. in processTiedPairs()
1672 for (MachineOperand &MO : MI->all_uses()) { in processTiedPairs()
1682 RemainingUses |= TRI->getSubRegIndexLaneMask(MO.getSubReg()); in processTiedPairs()
1689 LV->getVarInfo(RegB).removeKill(*MI)) { in processTiedPairs()
1691 --PrevMI; in processTiedPairs()
1692 LV->addVirtualRegisterKilled(RegB, *PrevMI); in processTiedPairs()
1700 SlotIndex UseIdx = LIS->getInstructionIndex(*MI); in processTiedPairs()
1707 if (S->end.getBaseIndex() != UseIdx) in processTiedPairs()
1709 S->end = LastCopyIdx; in processTiedPairs()
1713 LiveInterval &LI = LIS->getInterval(RegB); in processTiedPairs()
1725 for (MachineOperand &MO : MI->all_uses()) { in processTiedPairs()
1735 // RegA = STATEPOINT ... RegB(tied-def N)
1737 // RegB = STATEPOINT ... RegB(tied-def N)
1755 MachineOperand &DstMO = MI->getOperand(DstIdx); in processStatepoint()
1758 assert(RegB == MI->getOperand(SrcIdx).getReg()); in processStatepoint()
1764 // breaks assumption that statepoint kills tied-use register when in processStatepoint()
1769 const auto &UseLI = LIS->getInterval(RegB); in processStatepoint()
1770 const auto &DefLI = LIS->getInterval(RegA); in processStatepoint()
1777 } else if (LV && LV->getVarInfo(RegB).findKill(MI->getParent()) != MI) { in processStatepoint()
1780 // tied-use register will usually be found in preceeding deopt bundle. in processStatepoint()
1787 if (!MRI->constrainRegClass(RegB, MRI->getRegClass(RegA))) { in processStatepoint()
1794 MRI->replaceRegWith(RegA, RegB); in processStatepoint()
1797 VNInfo::Allocator &A = LIS->getVNInfoAllocator(); in processStatepoint()
1798 LiveInterval &LI = LIS->getInterval(RegB); in processStatepoint()
1799 LiveInterval &Other = LIS->getInterval(RegA); in processStatepoint()
1802 assert(VNI->id == NewVNIs.size() && "assumed"); in processStatepoint()
1806 VNInfo *VNI = NewVNIs[S.valno->id]; in processStatepoint()
1810 LIS->removeInterval(RegA); in processStatepoint()
1814 if (MI->getOperand(SrcIdx).isKill()) in processStatepoint()
1815 LV->removeVirtualRegisterKilled(RegB, *MI); in processStatepoint()
1816 LiveVariables::VarInfo &SrcInfo = LV->getVarInfo(RegB); in processStatepoint()
1817 LiveVariables::VarInfo &DstInfo = LV->getVarInfo(RegA); in processStatepoint()
1821 LV->addVirtualRegisterKilled(RegB, *KillMI, false); in processStatepoint()
1827 /// Reduce two-address instructions to two operands.
1831 LLVM_DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n"); in run()
1832 LLVM_DEBUG(dbgs() << "********** Function: " << MF->getName() << '\n'); in run()
1835 MRI->leaveSSA(); in run()
1837 // This pass will rewrite the tied-def to meet the RegConstraint. in run()
1838 MF->getProperties() in run()
1849 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end(); in run()
1853 if (mi->isDebugInstr()) { in run()
1860 if (mi->isRegSequence()) in run()
1884 = TiedOperands.begin()->second; in run()
1888 Register SrcReg = mi->getOperand(SrcIdx).getReg(); in run()
1889 Register DstReg = mi->getOperand(DstIdx).getReg(); in run()
1902 if (mi->getOpcode() == TargetOpcode::STATEPOINT && in run()
1917 if (mi->isInsertSubreg()) { in run()
1920 unsigned SubIdx = mi->getOperand(3).getImm(); in run()
1921 mi->removeOperand(3); in run()
1922 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx"); in run()
1923 mi->getOperand(0).setSubReg(SubIdx); in run()
1924 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef()); in run()
1925 mi->removeOperand(1); in run()
1926 mi->setDesc(TII->get(TargetOpcode::COPY)); in run()
1931 Register Reg = mi->getOperand(0).getReg(); in run()
1932 LiveInterval &LI = LIS->getInterval(Reg); in run()
1937 TRI->getSubRegIndexLaneMask(mi->getOperand(0).getSubReg()); in run()
1938 SlotIndex Idx = LIS->getInstructionIndex(*mi).getRegSlot(); in run()
1942 if (mi->getOperand(0).isUndef()) { in run()
1943 S.removeValNo(DefSeg->valno); in run()
1946 S.MergeValueNumberInto(DefSeg->valno, UseSeg->valno); in run()
1952 LIS->shrinkToUses(&LI); in run()
1956 LIS->removeInterval(Reg); in run()
1957 LIS->createAndComputeVirtRegInterval(Reg); in run()
1973 /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1975 /// The instruction is turned into a sequence of sub-register copies:
1994 if (LIS->hasInterval(DstReg)) { in eliminateRegSequence()
1995 DefVN = LIS->getInterval(DstReg) in eliminateRegSequence()
1996 .Query(LIS->getInstructionIndex(MI)) in eliminateRegSequence()
2009 UndefLanes |= TRI->getSubRegIndexLaneMask(SubIdx); in eliminateRegSequence()
2025 // Insert the sub-register copy. in eliminateRegSequence()
2027 TII->get(TargetOpcode::COPY)) in eliminateRegSequence()
2034 CopyMI->getOperand(0).setIsUndef(true); in eliminateRegSequence()
2042 LV->replaceKillInstruction(SrcReg, MI, *CopyMI); in eliminateRegSequence()
2052 MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); in eliminateRegSequence()
2053 for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j) in eliminateRegSequence()
2060 if (UndefLanes.any() && DefVN && MRI->shouldTrackSubRegLiveness(DstReg)) { in eliminateRegSequence()
2061 auto &LI = LIS->getInterval(DstReg); in eliminateRegSequence()
2062 for (MachineOperand &UseOp : MRI->use_operands(DstReg)) { in eliminateRegSequence()
2067 LI.getVNInfoAt(LIS->getInstructionIndex(*UseOp.getParent())); in eliminateRegSequence()
2070 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in eliminateRegSequence()
2074 LIS->removeInterval(DstReg); in eliminateRegSequence()
2076 LIS->RemoveMachineInstrFromMaps(MI); in eliminateRegSequence()
2085 LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs); in eliminateRegSequence()