Lines Matching +full:tri +full:- +full:default +full:- +full:2
1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
42 "disable-sched-hazard", cl::Hidden, cl::init(false),
45 TargetInstrInfo::~TargetInstrInfo() = default;
49 const TargetRegisterInfo *TRI, in getRegClass() argument
56 return TRI->getPointerRegClass(MF, RegClass); in getRegClass()
63 return TRI->getRegClass(RegClass); in getRegClass()
66 /// insertNoop - Insert a noop into the instruction stream at the specified
73 /// insertNoops - Insert noops into the instruction stream at the specified
91 /// Any other non-whitespace text is considered an instruction, with
93 /// Variable-length instructions are not handled here; this function
98 /// simple--i.e. not a logical or arithmetic expression--size values without
139 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
144 MachineBasicBlock *MBB = Tail->getParent(); in ReplaceTailWithBranchTo()
147 while (!MBB->succ_empty()) in ReplaceTailWithBranchTo()
148 MBB->removeSuccessor(MBB->succ_begin()); in ReplaceTailWithBranchTo()
151 DebugLoc DL = Tail->getDebugLoc(); in ReplaceTailWithBranchTo()
155 while (Tail != MBB->end()) { in ReplaceTailWithBranchTo()
157 if (MI->shouldUpdateCallSiteInfo()) in ReplaceTailWithBranchTo()
158 MBB->getParent()->eraseCallSiteInfo(&*MI); in ReplaceTailWithBranchTo()
159 MBB->erase(MI); in ReplaceTailWithBranchTo()
165 MBB->addSuccessor(NewDest); in ReplaceTailWithBranchTo()
227 CommutedMI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
228 CommutedMI->getOperand(0).setSubReg(SubReg0); in commuteInstructionImpl()
230 CommutedMI->getOperand(Idx2).setReg(Reg1); in commuteInstructionImpl()
231 CommutedMI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
232 CommutedMI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstructionImpl()
233 CommutedMI->getOperand(Idx1).setSubReg(SubReg2); in commuteInstructionImpl()
234 CommutedMI->getOperand(Idx2).setIsKill(Reg1IsKill); in commuteInstructionImpl()
235 CommutedMI->getOperand(Idx1).setIsKill(Reg2IsKill); in commuteInstructionImpl()
236 CommutedMI->getOperand(Idx2).setIsUndef(Reg1IsUndef); in commuteInstructionImpl()
237 CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef); in commuteInstructionImpl()
238 CommutedMI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal); in commuteInstructionImpl()
239 CommutedMI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal); in commuteInstructionImpl()
243 CommutedMI->getOperand(Idx2).setIsRenamable(Reg1IsRenamable); in commuteInstructionImpl()
245 CommutedMI->getOperand(Idx1).setIsRenamable(Reg2IsRenamable); in commuteInstructionImpl()
367 if ((*o)->isLoad() && in hasLoadFromStackSlot()
368 isa_and_nonnull<FixedStackPseudoSourceValue>((*o)->getPseudoValue())) in hasLoadFromStackSlot()
381 if ((*o)->isStore() && in hasStoreToStackSlot()
382 isa_and_nonnull<FixedStackPseudoSourceValue>((*o)->getPseudoValue())) in hasStoreToStackSlot()
392 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in getStackSlotRange() local
394 Size = TRI->getSpillSize(*RC); in getStackSlotRange()
398 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx); in getStackSlotRange()
403 int BitOffset = TRI->getSubRegIdxOffset(SubIdx); in getStackSlotRange()
410 assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range"); in getStackSlotRange()
413 Offset = TRI->getSpillSize(*RC) - (Offset + Size); in getStackSlotRange()
422 const TargetRegisterInfo &TRI) const { in reMaterialize()
423 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig); in reMaterialize()
424 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
439 // CFI instructions are marked as non-duplicable, because Darwin compact in duplicate()
455 if (MI.getNumOperands() != 2) in canFoldCopy()
457 assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand"); in canFoldCopy()
460 const MachineOperand &LiveOp = MI.getOperand(1 - FoldIdx); in canFoldCopy()
470 const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo(); in canFoldCopy()
474 return RC->contains(LiveOp.getReg()) ? RC : nullptr; in canFoldCopy()
476 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) in canFoldCopy()
498 default: in getPatchpointUnfoldableRange()
560 --TiedTo; in foldPatchpoint()
561 NewMI->tieOperands(TiedTo, NewMI->getNumOperands() - 1); in foldPatchpoint()
571 if (MI->getOperand(OpNo).isTied()) { in foldInlineAsmMemOperand()
572 unsigned TiedTo = MI->findTiedOperandIdx(OpNo); in foldInlineAsmMemOperand()
573 MI->untieRegOperand(OpNo); in foldInlineAsmMemOperand()
581 MI->removeOperand(OpNo); in foldInlineAsmMemOperand()
582 MI->insert(MI->operands_begin() + OpNo, NewOps); in foldInlineAsmMemOperand()
585 // is the per-target number of operands that represent the memory operand in foldInlineAsmMemOperand()
589 MachineOperand &MD = MI->getOperand(OpNo - 1); in foldInlineAsmMemOperand()
602 assert(MI.getOperand(Op).isReg() && "shouldn't be folding non-reg operands"); in foldInlineAsmMemOperand()
625 const MachineFrameInfo &MFI = MF->getFrameInfo(); in foldInlineAsmMemOperand()
626 MachineMemOperand *MMO = MF->getMachineMemOperand( in foldInlineAsmMemOperand()
645 MachineFunction &MF = *MBB->getParent(); in foldMemoryOperand()
652 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in foldMemoryOperand() local
661 unsigned SubRegSize = TRI->getSubRegIdxSize(SubReg); in foldMemoryOperand()
670 assert(MemSize && "Did not expect a zero-sized stack slot"); in foldMemoryOperand()
680 MBB->insert(MI, NewMI); in foldMemoryOperand()
689 NewMI->setMemRefs(MF, MI.memoperands()); in foldMemoryOperand()
692 NewMI->mayStore()) && in foldMemoryOperand()
693 "Folded a def to a non-store!"); in foldMemoryOperand()
695 NewMI->mayLoad()) && in foldMemoryOperand()
696 "Folded a use to a non-load!"); in foldMemoryOperand()
697 assert(MFI.getObjectOffset(FI) != -1); in foldMemoryOperand()
701 NewMI->addMemOperand(MF, MMO); in foldMemoryOperand()
705 NewMI->cloneInstrSymbols(MF, MI); in foldMemoryOperand()
718 const MachineOperand &MO = MI.getOperand(1 - Ops[0]); in foldMemoryOperand()
722 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI, in foldMemoryOperand()
725 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI, Register()); in foldMemoryOperand()
726 return &*--Pos; in foldMemoryOperand()
766 NewMI->setMemRefs(MF, LoadMI.memoperands()); in foldMemoryOperand()
769 NewMI->setMemRefs(MF, MI.memoperands()); in foldMemoryOperand()
773 NewMI->addMemOperand(MF, *I); in foldMemoryOperand()
779 /// transferImplicitOperands - MI is a pseudo-instruction, and the lowered
783 const TargetRegisterInfo *TRI) { in transferImplicitOperands() argument
785 --CopyMI; in transferImplicitOperands()
787 Register DstReg = MI->getOperand(0).getReg(); in transferImplicitOperands()
788 for (const MachineOperand &MO : MI->implicit_operands()) { in transferImplicitOperands()
789 CopyMI->addOperand(MO); in transferImplicitOperands()
792 // involved. If there was implicit kill of a super-register overlapping the in transferImplicitOperands()
795 if (MO.isKill() && TRI->regsOverlap(DstReg, MO.getReg())) in transferImplicitOperands()
796 CopyMI->getOperand(CopyMI->getNumOperands() - 1).setIsKill(false); in transferImplicitOperands()
801 const TargetRegisterInfo *TRI) const { in lowerCopy()
802 if (MI->allDefsAreDead()) { in lowerCopy()
803 MI->setDesc(get(TargetOpcode::KILL)); in lowerCopy()
807 MachineOperand &DstMO = MI->getOperand(0); in lowerCopy()
808 MachineOperand &SrcMO = MI->getOperand(1); in lowerCopy()
814 if (SrcMO.isUndef() || MI->getNumOperands() > 2) { in lowerCopy()
815 // We must make sure the super-register gets killed. Replace the in lowerCopy()
817 MI->setDesc(get(TargetOpcode::KILL)); in lowerCopy()
821 MI->eraseFromParent(); in lowerCopy()
825 copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), DstMO.getReg(), in lowerCopy()
828 if (MI->getNumOperands() > 2) in lowerCopy()
829 transferImplicitOperands(MI, TRI); in lowerCopy()
830 MI->eraseFromParent(); in lowerCopy()
836 const MachineOperand &Op2 = Inst.getOperand(2); in hasReassociableOperands()
837 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in hasReassociableOperands()
849 return MI1 && MI2 && (MI1->getParent() == MBB || MI2->getParent() == MBB); in hasReassociableOperands()
860 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in hasReassociableSibling()
862 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling()
867 Commuted = !areOpcodesEqualOrInverse(Opcode, MI1->getOpcode()) && in hasReassociableSibling()
868 areOpcodesEqualOrInverse(Opcode, MI2->getOpcode()); in hasReassociableSibling()
873 // 2. The previous instruction must also be associative/commutative or be the in hasReassociableSibling()
875 // instructions with the same opcode if traits like fast-math-flags are in hasReassociableSibling()
880 return areOpcodesEqualOrInverse(Opcode, MI1->getOpcode()) && in hasReassociableSibling()
884 MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg()); in hasReassociableSibling()
889 // 2. The instruction must have virtual register definitions for its
906 // -->
912 // parallel (or back-to-back in a pipeline) instead of depending on each other.
917 // 2. Only enable at -O3 or some other non-default optimization level.
918 // 3. Pre-screen pattern candidates here: if an operand of the previous
950 return CombinerObjective::Default; in getCombinerObjective()
980 // operation, `-` is the inverse): in getReassociationOpcodes()
983 // (A + X) - Y => A + (X - Y) in getReassociationOpcodes()
984 // (A - X) + Y => A - (X - Y) in getReassociationOpcodes()
985 // (A - X) - Y => A - (X + Y) in getReassociationOpcodes()
988 // (X + A) - Y => (X - Y) + A in getReassociationOpcodes()
989 // (X - A) + Y => (X + Y) - A in getReassociationOpcodes()
990 // (X - A) - Y => (X - Y) - A in getReassociationOpcodes()
993 // Y - (A + X) => (Y - X) - A in getReassociationOpcodes()
994 // Y + (A - X) => (Y - X) + A in getReassociationOpcodes()
995 // Y - (A - X) => (Y + X) - A in getReassociationOpcodes()
998 // Y - (X + A) => (Y - X) - A in getReassociationOpcodes()
999 // Y + (X - A) => (Y + X) - A in getReassociationOpcodes()
1000 // Y - (X - A) => (Y - X) + A in getReassociationOpcodes()
1002 default: in getReassociationOpcodes()
1045 default: in mustSwapOperands()
1063 OperandIndices = {1, 1, 1, 2, 2}; in getReassociateOperandIndices()
1066 OperandIndices = {2, 1, 2, 2, 1}; in getReassociateOperandIndices()
1069 OperandIndices = {1, 2, 1, 1, 2}; in getReassociateOperandIndices()
1072 OperandIndices = {2, 2, 2, 1, 1}; in getReassociateOperandIndices()
1074 default: in getReassociateOperandIndices()
1088 MachineRegisterInfo &MRI = MF->getRegInfo(); in reassociateOps()
1089 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); in reassociateOps()
1090 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); in reassociateOps() local
1091 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI); in reassociateOps()
1094 MachineOperand &OpB = Root.getOperand(OperandIndices[2]); in reassociateOps()
1141 RootFirstOpIdx = OperandIndices[2]; in reassociateOps()
1148 RootSecondOpIdx = OperandIndices[2]; in reassociateOps()
1153 RootFirstOpIdx = OperandIndices[2]; in reassociateOps()
1160 RootSecondOpIdx = OperandIndices[2]; in reassociateOps()
1162 default: in reassociateOps()
1166 // Basically BuildMI but doesn't add implicit operands by default. in reassociateOps()
1177 buildMINoImplicit(*MF, MIMetadata(Prev), TII->get(NewPrevOpc), NewVR); in reassociateOps()
1198 buildMINoImplicit(*MF, MIMetadata(Root), TII->get(NewRootOpc), RegC); in reassociateOps()
1214 // But clear poison-generating flags because those may not be valid now. in reassociateOps()
1215 // TODO: There should be a helper function for copying only fast-math-flags. in reassociateOps()
1217 MIB1->setFlags(IntersectedFlags); in reassociateOps()
1218 MIB1->clearFlag(MachineInstr::MIFlag::NoSWrap); in reassociateOps()
1219 MIB1->clearFlag(MachineInstr::MIFlag::NoUWrap); in reassociateOps()
1220 MIB1->clearFlag(MachineInstr::MIFlag::IsExact); in reassociateOps()
1222 MIB2->setFlags(IntersectedFlags); in reassociateOps()
1223 MIB2->clearFlag(MachineInstr::MIFlag::NoSWrap); in reassociateOps()
1224 MIB2->clearFlag(MachineInstr::MIFlag::NoUWrap); in reassociateOps()
1225 MIB2->clearFlag(MachineInstr::MIFlag::IsExact); in reassociateOps()
1244 MIB2.getInstr()->setDebugInstrNum(OldRootNum); in reassociateOps()
1252 MachineRegisterInfo &MRI = Root.getMF()->getRegInfo(); in genAlternativeCodeSequence()
1261 if (Prev->getParent() != Root.getParent()) in genAlternativeCodeSequence()
1282 // A sub-register definition can only be rematerialized if the instruction in isReallyTriviallyReMaterializable()
1284 // read-modify-write operation on the full virtual register which cannot be in isReallyTriviallyReMaterializable()
1291 // redundant with subsequent checks, but it's target-independent, in isReallyTriviallyReMaterializable()
1312 // If any of the registers accessed are non-constant, conservatively assume in isReallyTriviallyReMaterializable()
1320 // Check for a well-behaved physical register. in isReallyTriviallyReMaterializable()
1335 // Only allow one virtual-register def. There may be multiple defs of the in isReallyTriviallyReMaterializable()
1340 // Don't allow any virtual-register uses. Rematting an instruction with in isReallyTriviallyReMaterializable()
1353 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); in getSPAdjust()
1355 TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown; in getSPAdjust()
1363 int SPAdj = TFI->alignSPAdjust(getFrameSize(MI)); in getSPAdjust()
1367 SPAdj = -SPAdj; in getSPAdjust()
1372 /// isSchedulingBoundary - Test if the given instruction should be
1387 // a stack-oriented pointer, as it's unlikely to be profitable. This in isSchedulingBoundary()
1392 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in isSchedulingBoundary() local
1393 return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI); in isSchedulingBoundary()
1402 // Default implementation of CreateTargetRAHazardRecognizer.
1410 // Default implementation of CreateTargetMIHazardRecognizer.
1413 return new ScoreboardHazardRecognizer(II, DAG, "machine-scheduler"); in CreateTargetMIHazardRecognizer()
1416 // Default implementation of CreateTargetPostRAHazardRecognizer.
1420 return new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched"); in CreateTargetPostRAHazardRecognizer()
1423 // Default implementation of getMemOperandWithOffset.
1426 bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const { in getMemOperandWithOffset()
1430 Width, TRI) || in getMemOperandWithOffset()
1437 //===----------------------------------------------------------------------===//
1439 //===----------------------------------------------------------------------===//
1445 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
1448 if (!DefNode->isMachineOpcode()) in getOperandLatency()
1451 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
1452 if (!UseNode->isMachineOpcode()) in getOperandLatency()
1453 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1454 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
1455 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1460 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
1463 if (!N->isMachineOpcode()) in getInstrLatency()
1466 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
1469 //===----------------------------------------------------------------------===//
1471 //===----------------------------------------------------------------------===//
1475 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
1479 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
1483 // The # of u-ops is dynamically determined. The specific target should in getNumMicroOps()
1488 /// Return the default expected latency for a def based on it's opcode.
1507 // Default to one cycle for no itinerary. However, an "empty" itinerary may in getInstrLatency()
1510 return MI.mayLoad() ? 2 : 1; in getInstrLatency()
1512 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrLatency()
1519 if (!ItinData || ItinData->isEmpty()) in hasLowDefLatency()
1524 ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1551 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); in describeLoadedValue() local
1552 DIExpression *Expr = DIExpression::get(MF->getFunction().getContext(), {}); in describeLoadedValue()
1556 // To simplify the sub-register handling, verify that we only need to in describeLoadedValue()
1558 assert(MF->getProperties().hasProperty( in describeLoadedValue()
1562 Register DestReg = DestSrc->Destination->getReg(); in describeLoadedValue()
1570 return ParamLoadedValue(*DestSrc->Source, Expr); in describeLoadedValue()
1575 Register SrcReg = RegImm->Reg; in describeLoadedValue()
1576 Offset = RegImm->Imm; in describeLoadedValue()
1583 const auto &TII = MF->getSubtarget().getInstrInfo(); in describeLoadedValue()
1584 const MachineFrameInfo &MFI = MF->getFrameInfo(); in describeLoadedValue()
1586 const PseudoSourceValue *PSV = MMO->getPseudoValue(); in describeLoadedValue()
1589 // sufficient to check that it isn't aliased by any high-level IR value. in describeLoadedValue()
1590 if (!PSV || PSV->mayAlias(&MFI)) in describeLoadedValue()
1594 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in describeLoadedValue()
1595 TRI)) in describeLoadedValue()
1605 // DIV64m $rsp, 1, $noreg, 24, $noreg, implicit-def dead $rax, implicit-def $rdx in describeLoadedValue()
1616 Ops.push_back(MMO->getSize().hasValue() ? MMO->getSize().getValue() in describeLoadedValue()
1629 for (auto &AdjI : reverse(make_range(MBB->instr_begin(), MI.getIterator()))) { in getCallFrameSizeAt()
1638 return MBB->getCallFrameSize(); in getCallFrameSizeAt()
1641 /// Both DefMI and UseMI must be valid. By default, call directly to the
1648 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1664 OpIdx += 2) { in getRegSequenceInputs()
1693 const MachineOperand &MOSubIdx = MI.getOperand(2); in getExtractSubregInputs()
1716 const MachineOperand &MOInsertedReg = MI.getOperand(2); in getInsertSubregInputs()
1734 const TargetRegisterInfo *TRI) const { in createMIROperandComment()
1768 if (TRI) { in createMIROperandComment()
1769 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in createMIROperandComment()
1790 TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo() = default;
1799 const Function &ParentFn = FirstCand.getMF()->getFunction(); in mergeOutliningCandidateAttributes()
1800 if (ParentFn.hasFnAttribute("target-features")) in mergeOutliningCandidateAttributes()
1801 F.addFnAttr(ParentFn.getFnAttribute("target-features")); in mergeOutliningCandidateAttributes()
1802 if (ParentFn.hasFnAttribute("target-cpu")) in mergeOutliningCandidateAttributes()
1803 F.addFnAttr(ParentFn.getFnAttribute("target-cpu")); in mergeOutliningCandidateAttributes()
1807 return C.getMF()->getFunction().hasFnAttribute(Attribute::NoUnwind); in mergeOutliningCandidateAttributes()
1817 // have support for outlining those. Special-case that here. in getOutliningType()
1841 default: in getOutliningType()
1848 if (!MI.getParent()->succ_empty()) in getOutliningType()
1864 // There was one exception (RISC-V), but MO_TargetIndex also isn't used there. in getOutliningType()
1865 // As such, this check is removed both here and in the target-specific in getOutliningType()
1867 // catch anyone off-guard somewhere down the line. in getOutliningType()
1885 // If we don't know, delegate to the target-specific hook. in getOutliningType()
1897 if (First->getOpcode() == TargetOpcode::FENTRY_CALL || in isMBBSafeToOutlineFrom()
1898 First->getOpcode() == TargetOpcode::PATCHABLE_FUNCTION_ENTER) in isMBBSafeToOutlineFrom()
1901 // Some instrumentations create special pseudo-instructions at or just before in isMBBSafeToOutlineFrom()
1904 if (Last->getOpcode() == TargetOpcode::PATCHABLE_RET || in isMBBSafeToOutlineFrom()
1905 Last->getOpcode() == TargetOpcode::PATCHABLE_TAIL_CALL) in isMBBSafeToOutlineFrom()
1908 if (Last != First && Last->isReturn()) { in isMBBSafeToOutlineFrom()
1909 --Last; in isMBBSafeToOutlineFrom()
1910 if (Last->getOpcode() == TargetOpcode::PATCHABLE_FUNCTION_EXIT || in isMBBSafeToOutlineFrom()
1911 Last->getOpcode() == TargetOpcode::PATCHABLE_TAIL_CALL) in isMBBSafeToOutlineFrom()