Lines Matching refs:DemandedRHS
1350 APInt DemandedLHS, DemandedRHS; in SimplifyDemandedBits() local
1352 DemandedRHS)) in SimplifyDemandedBits()
1355 if (!!DemandedLHS || !!DemandedRHS) { in SimplifyDemandedBits()
1367 if (!!DemandedRHS) { in SimplifyDemandedBits()
1368 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedRHS, Known2, TLO, in SimplifyDemandedBits()
1378 Op1, DemandedBits, DemandedRHS, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
3424 APInt DemandedRHS(DemandedElts); in SimplifyDemandedVectorElts() local
3430 if (SimplifyDemandedVectorElts(RHS, DemandedRHS, UndefRHS, ZeroRHS, TLO, in SimplifyDemandedVectorElts()
3454 APInt DemandedRHS(NumElts, 0); in SimplifyDemandedVectorElts() local
3463 DemandedRHS.setBit(M - NumElts); in SimplifyDemandedVectorElts()
3472 if (SimplifyDemandedVectorElts(RHS, DemandedRHS, UndefRHS, ZeroRHS, TLO, in SimplifyDemandedVectorElts()