Lines Matching refs:DCI
621 DAGCombinerInfo &DCI) const { in SimplifyDemandedBits()
622 SelectionDAG &DAG = DCI.DAG; in SimplifyDemandedBits()
623 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
624 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
629 DCI.AddToWorklist(Op.getNode()); in SimplifyDemandedBits()
630 DCI.CommitTargetLoweringOpt(TLO); in SimplifyDemandedBits()
637 DAGCombinerInfo &DCI) const { in SimplifyDemandedBits()
638 SelectionDAG &DAG = DCI.DAG; in SimplifyDemandedBits()
639 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
640 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
646 DCI.AddToWorklist(Op.getNode()); in SimplifyDemandedBits()
647 DCI.CommitTargetLoweringOpt(TLO); in SimplifyDemandedBits()
2977 DAGCombinerInfo &DCI) const { in SimplifyDemandedVectorElts()
2978 SelectionDAG &DAG = DCI.DAG; in SimplifyDemandedVectorElts()
2979 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedVectorElts()
2980 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedVectorElts()
2986 DCI.AddToWorklist(Op.getNode()); in SimplifyDemandedVectorElts()
2987 DCI.CommitTargetLoweringOpt(TLO); in SimplifyDemandedVectorElts()
3978 DAGCombinerInfo &DCI) const { in foldSetCCWithAnd()
3982 SelectionDAG &DAG = DCI.DAG; in foldSetCCWithAnd()
4045 if (DCI.isBeforeLegalizeOps() || in foldSetCCWithAnd()
4080 EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI, in optimizeSetCCOfSignedTruncationCheck() argument
4149 SelectionDAG &DAG = DCI.DAG; in optimizeSetCCOfSignedTruncationCheck()
4165 DAGCombinerInfo &DCI, const SDLoc &DL) const { in optimizeSetCCByHoistingAndByConstFromLogicalShift() argument
4174 SelectionDAG &DAG = DCI.DAG; in optimizeSetCCByHoistingAndByConstFromLogicalShift()
4237 DAGCombinerInfo &DCI) const { in foldSetCCWithBinOp()
4246 SelectionDAG &DAG = DCI.DAG; in foldSetCCWithBinOp()
4268 if (!DCI.isCalledByLegalizer()) in foldSetCCWithBinOp()
4269 DCI.AddToWorklist(YShl1.getNode()); in foldSetCCWithBinOp()
4460 DAGCombinerInfo &DCI, in SimplifySetCC() argument
4462 SelectionDAG &DAG = DCI.DAG; in SimplifySetCC()
4482 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4491 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4560 DCI.isBeforeLegalize() && N0->hasOneUse()) { in SimplifySetCC()
4647 if (DCI.isBeforeLegalize() && in SimplifySetCC()
4755 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4789 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
4790 DCI.AddToWorklist(ZextOp.getNode()); in SimplifySetCC()
4811 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4912 optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
4941 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4961 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4977 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4995 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
5012 VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
5080 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
5204 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
5265 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
5351 if (SDValue V = foldSetCCWithBinOp(VT, N0, N1, Cond, dl, DCI)) in SimplifySetCC()
5357 if (SDValue V = foldSetCCWithBinOp(VT, N1, N0, Cond, dl, DCI)) in SimplifySetCC()
5360 if (SDValue V = foldSetCCWithAnd(VT, N0, N1, Cond, dl, DCI)) in SimplifySetCC()
5371 if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
5374 if (SDValue Folded = buildSREMEqFold(VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
5388 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5389 DCI.AddToWorklist(Temp.getNode()); in SimplifySetCC()
5398 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5399 DCI.AddToWorklist(Temp.getNode()); in SimplifySetCC()
5405 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5406 DCI.AddToWorklist(Temp.getNode()); in SimplifySetCC()
5412 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5413 DCI.AddToWorklist(Temp.getNode()); in SimplifySetCC()
5422 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5423 DCI.AddToWorklist(N0.getNode()); in SimplifySetCC()
5468 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
6674 DAGCombinerInfo &DCI, in buildUREMEqFold() argument
6678 DCI, DL, Built)) { in buildUREMEqFold()
6680 DCI.AddToWorklist(N); in buildUREMEqFold()
6690 DAGCombinerInfo &DCI, const SDLoc &DL, in prepareUREMEqFold() argument
6700 SelectionDAG &DAG = DCI.DAG; in prepareUREMEqFold()
6708 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareUREMEqFold()
6842 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::SUB, VT)) in prepareUREMEqFold()
6857 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareUREMEqFold()
6914 DAGCombinerInfo &DCI, in buildSREMEqFold() argument
6918 DCI, DL, Built)) { in buildSREMEqFold()
6921 DCI.AddToWorklist(N); in buildSREMEqFold()
6931 DAGCombinerInfo &DCI, const SDLoc &DL, in prepareSREMEqFold() argument
6958 SelectionDAG &DAG = DCI.DAG; in prepareSREMEqFold()
6967 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareSREMEqFold()
7127 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ADD, VT)) in prepareSREMEqFold()
7139 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareSREMEqFold()