158   for (SDep &Pred : SU->Preds) {  in ReleasePredecessors()
159     ReleasePred(SU, &Pred);  in ReleasePredecessors()
160     if (Pred.isAssignedRegDep()) {  in ReleasePredecessors()
165       if (!LiveRegDefs[Pred.getReg()]) {  in ReleasePredecessors()
167         LiveRegDefs[Pred.getReg()] = Pred.getSUnit();  in ReleasePredecessors()
168         LiveRegCycles[Pred.getReg()] = CurCycle;  in ReleasePredecessors()
278     for (SDep &Pred : SU->Preds) {  in CopyAndMoveSuccessors()
279       if (Pred.isCtrl())  in CopyAndMoveSuccessors()
280         ChainPred = Pred;  in CopyAndMoveSuccessors()
281       else if (Pred.getSUnit()->getNode() &&  in CopyAndMoveSuccessors()
282                Pred.getSUnit()->getNode()->isOperandOf(LoadNode))  in CopyAndMoveSuccessors()
283         LoadPreds.push_back(Pred);  in CopyAndMoveSuccessors()
285         NodePreds.push_back(Pred);  in CopyAndMoveSuccessors()
299     for (const SDep &Pred : LoadPreds) {  in CopyAndMoveSuccessors()  local
300       RemovePred(SU, Pred);  in CopyAndMoveSuccessors()
302         AddPred(LoadSU, Pred);  in CopyAndMoveSuccessors()
305     for (const SDep &Pred : NodePreds) {  in CopyAndMoveSuccessors()  local
306       RemovePred(SU, Pred);  in CopyAndMoveSuccessors()
307       AddPred(NewSU, Pred);  in CopyAndMoveSuccessors()
344   for (SDep &Pred : SU->Preds)  in CopyAndMoveSuccessors()
345     if (!Pred.isArtificial())  in CopyAndMoveSuccessors()
346       AddPred(NewSU, Pred);  in CopyAndMoveSuccessors()
479   for (SDep &Pred : SU->Preds) {  in DelayForLiveRegsBottomUp()
480     if (Pred.isAssignedRegDep()) {  in DelayForLiveRegsBottomUp()
481       CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs,  in DelayForLiveRegsBottomUp()