Lines Matching refs:RC
59 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue() local
60 RegLimit[RC->getID()] = TRI->getRegPressureLimit(RC, *IS->MF); in ResourcePriorityQueue()
359 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta() local
360 RegBalance += rawRegPressureDelta(SU, RC->getID()); in regPressureDelta()
363 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta() local
364 if ((RegPressure[RC->getID()] + in regPressureDelta()
365 rawRegPressureDelta(SU, RC->getID()) > 0) && in regPressureDelta()
366 (RegPressure[RC->getID()] + in regPressureDelta()
367 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) in regPressureDelta()
368 RegBalance += rawRegPressureDelta(SU, RC->getID()); in regPressureDelta()
477 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
478 if (RC) in scheduledNode()
479 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID()); in scheduledNode()
488 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
489 if (RC) { in scheduledNode()
490 if (RegPressure[RC->getID()] > in scheduledNode()
491 (numberRCValPredInSU(SU, RC->getID()))) in scheduledNode()
492 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID()); in scheduledNode()
493 else RegPressure[RC->getID()] = 0; in scheduledNode()