Lines Matching +full:clear +full:- +full:bit
1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
41 #define DEBUG_TYPE "function-lowering-info"
43 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
47 if (I->use_empty()) return false; in isUsedOutsideOfDefiningBlock()
49 const BasicBlock *BB = I->getParent(); in isUsedOutsideOfDefiningBlock()
50 for (const User *U : I->users()) in isUsedOutsideOfDefiningBlock()
51 if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U)) in isUsedOutsideOfDefiningBlock()
67 for (const Use &U : I->uses()) { in getPreferredExtendForValue()
69 NumOfSigned += CI->isSigned(); in getPreferredExtendForValue()
70 NumOfUnsigned += CI->isUnsigned(); in getPreferredExtendForValue()
73 if (!CallI->isArgOperand(&U)) in getPreferredExtendForValue()
75 unsigned ArgNo = CallI->getArgOperandNo(&U); in getPreferredExtendForValue()
76 NumOfUnsigned += CallI->paramHasAttr(ArgNo, Attribute::ZExt); in getPreferredExtendForValue()
77 NumOfSigned += CallI->paramHasAttr(ArgNo, Attribute::SExt); in getPreferredExtendForValue()
90 TLI = MF->getSubtarget().getTargetLowering(); in set()
91 RegInfo = &MF->getRegInfo(); in set()
92 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); in set()
93 UA = DAG->getUniformityInfo(); in set()
95 // Check whether the function can return without sret-demotion. in set()
97 CallingConv::ID CC = Fn->getCallingConv(); in set()
99 GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI, in set()
102 TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext()); in set()
104 // If this personality uses funclets, we need to do a bit more work. in set()
107 Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr); in set()
110 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo(); in set()
122 CatchObjects.insert({AI, {}}).first->second.push_back( in set()
133 const Align StackAlign = TFI->getStackAlign(); in set()
137 Type *Ty = AI->getAllocatedType(); in set()
138 Align Alignment = AI->getAlign(); in set()
143 if (AI->isStaticAlloca() && in set()
144 (TFI->isStackRealignable() || (Alignment <= StackAlign))) { in set()
145 const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize()); in set()
147 MF->getDataLayout().getTypeAllocSize(Ty).getKnownMinValue(); in set()
149 TySize *= CUI->getZExtValue(); // Get total allocated size. in set()
150 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. in set()
153 if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) { in set()
154 FrameIndex = MF->getFrameInfo().CreateFixedObject( in set()
156 MF->getFrameInfo().setObjectAlignment(FrameIndex, Alignment); in set()
158 FrameIndex = MF->getFrameInfo().CreateStackObject(TySize, Alignment, in set()
165 if (Ty->isScalableTy()) in set()
166 MF->getFrameInfo().setStackID(FrameIndex, in set()
167 TFI->getStackIDForScalableVectors()); in set()
172 for (int *CatchObjPtr : Iter->second) in set()
179 // Inform the Frame Information that we have variable-sized objects. in set()
180 MF->getFrameInfo().CreateVariableSizedObject( in set()
185 if (Call->isInlineAsm()) { in set()
186 Register SP = TLI->getStackPointerRegisterToSaveRestore(); in set()
187 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); in set()
189 TLI->ParseConstraints(Fn->getDataLayout(), TRI, in set()
194 TLI->ComputeConstraintToUse(Op, SDValue(), DAG); in set()
196 TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode, in set()
199 MF->getFrameInfo().setHasOpaqueSPAdjustment(true); in set()
207 if (II->getIntrinsicID() == Intrinsic::vastart) in set()
208 MF->getFrameInfo().setHasVAStart(true); in set()
214 if (CI->isMustTailCall() && Fn->isVarArg()) in set()
215 MF->getFrameInfo().setHasMustTailInVarArgFunc(true); in set()
219 if (Call->hasFnAttr(Attribute::ReturnsTwice)) in set()
220 MF->setExposesReturnsTwice(true); in set()
231 if (DAG->getOptLevel() != CodeGenOptLevel::None) in set()
244 // If this is a non-landingpad EH pad, mark this function as using in set()
249 MF->setHasEHScopes(true); in set()
250 MF->setHasEHFunclets(true); in set()
251 MF->getFrameInfo().setHasOpaqueSPAdjustment(true); in set()
265 MF->push_back(MBB); in set()
267 // Transfer the address-taken flag. This is necessary because there could in set()
271 MBB->setAddressTakenIRBlock(const_cast<BasicBlock *>(&BB)); in set()
275 MBB->setIsEHPad(); in set()
284 if (PN.getType()->isEmptyTy()) in set()
292 ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs); in set()
294 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT); in set()
295 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); in set()
297 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i); in set()
304 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo(); in set()
325 WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo(); in set()
348 /// clear - Clear out all the function-specific state. This returns this
351 void FunctionLoweringInfo::clear() { in clear() function in FunctionLoweringInfo
352 MBBMap.clear(); in clear()
353 ValueMap.clear(); in clear()
354 VirtReg2Value.clear(); in clear()
355 StaticAllocaMap.clear(); in clear()
356 LiveOutRegInfo.clear(); in clear()
357 VisitedBBs.clear(); in clear()
358 ArgDbgValues.clear(); in clear()
359 DescribedArgs.clear(); in clear()
360 ByValArgFrameIndexMap.clear(); in clear()
361 RegFixups.clear(); in clear()
362 RegsWithFixups.clear(); in clear()
363 StatepointStackSlots.clear(); in clear()
364 StatepointRelocationMaps.clear(); in clear()
365 PreferredExtendType.clear(); in clear()
366 PreprocessedDbgDeclares.clear(); in clear()
367 PreprocessedDVRDeclares.clear(); in clear()
370 /// CreateReg - Allocate a single virtual register for the given type.
372 return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT, isDivergent)); in CreateReg()
375 /// CreateRegs - Allocate the appropriate number of virtual registers of
384 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); in CreateRegs()
388 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
390 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
400 return CreateRegs(V->getType(), UA && UA->isDivergent(V) && in CreateRegs()
401 !TLI->requiresUniformRegister(*MF, V)); in CreateRegs()
406 if (V->getType()->isTokenTy() && !isa<ConvergenceControlInst>(V)) in InitializeRegForValue()
414 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
416 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
417 /// the larger bit width by zero extension. The bit width must be no smaller
418 /// than the LiveOutInfo's existing bit width.
425 if (!LOI->IsValid) in GetLiveOutRegInfo()
428 if (BitWidth > LOI->Known.getBitWidth()) { in GetLiveOutRegInfo()
429 LOI->NumSignBits = 1; in GetLiveOutRegInfo()
430 LOI->Known = LOI->Known.anyext(BitWidth); in GetLiveOutRegInfo()
436 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
439 Type *Ty = PN->getType(); in ComputePHILiveOutRegInfo()
440 if (!Ty->isIntegerTy() || Ty->isVectorTy()) in ComputePHILiveOutRegInfo()
444 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); in ComputePHILiveOutRegInfo()
446 "PHIs with non-vector integer types should have a single VT."); in ComputePHILiveOutRegInfo()
449 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
451 IntVT = TLI->getRegisterType(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
458 Register DestReg = It->second; in ComputePHILiveOutRegInfo()
465 Value *V = PN->getIncomingValue(0); in ComputePHILiveOutRegInfo()
474 if (TLI->signExtendConstant(CI)) in ComputePHILiveOutRegInfo()
475 Val = CI->getValue().sext(BitWidth); in ComputePHILiveOutRegInfo()
477 Val = CI->getValue().zext(BitWidth); in ComputePHILiveOutRegInfo()
498 "Masks should have the same bit width as the type."); in ComputePHILiveOutRegInfo()
500 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) { in ComputePHILiveOutRegInfo()
501 Value *V = PN->getIncomingValue(i); in ComputePHILiveOutRegInfo()
510 if (TLI->signExtendConstant(CI)) in ComputePHILiveOutRegInfo()
511 Val = CI->getValue().sext(BitWidth); in ComputePHILiveOutRegInfo()
513 Val = CI->getValue().zext(BitWidth); in ComputePHILiveOutRegInfo()
532 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits); in ComputePHILiveOutRegInfo()
533 DestLOI.Known = DestLOI.Known.intersectWith(SrcLOI->Known); in ComputePHILiveOutRegInfo()
537 /// setArgumentFrameIndex - Record frame index for the byval
545 /// getArgumentFrameIndex - Get frame index for the byval argument.
551 return I->second; in getArgumentFrameIndex()
558 MachineRegisterInfo &MRI = MF->getRegInfo(); in getCatchPadExceptionPointerVReg()
560 Register &VReg = I.first->second; in getCatchPadExceptionPointerVReg()
572 ValueVTs.clear(); in getValueFromVirtualReg()
573 ComputeValueVTs(*TLI, Fn->getDataLayout(), in getValueFromVirtualReg()
574 P.first->getType(), ValueVTs); in getValueFromVirtualReg()
577 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT); in getValueFromVirtualReg()