Lines Matching refs:CC1

1273         ISD::CondCode CC1 = cast<CondCodeSDNode>(N1.getOperand(2))->get();  in reassociateOpsCommutative()  local
1276 if (CC1 == CC00 && CC1 != CC01) { in reassociateOpsCommutative()
1280 if (CC1 == CC01 && CC1 != CC00) { in reassociateOpsCommutative()
5966 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get(); in foldLogicOfSetCCs() local
5968 if (LR == RR && CC0 == CC1 && IsInteger) { in foldLogicOfSetCCs()
5973 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero; in foldLogicOfSetCCs()
5975 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1; in foldLogicOfSetCCs()
5977 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero; in foldLogicOfSetCCs()
5979 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero; in foldLogicOfSetCCs()
5988 return DAG.getSetCC(DL, VT, Or, LR, CC1); in foldLogicOfSetCCs()
5992 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1; in foldLogicOfSetCCs()
5994 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero; in foldLogicOfSetCCs()
5996 bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1; in foldLogicOfSetCCs()
5998 bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1; in foldLogicOfSetCCs()
6007 return DAG.getSetCC(DL, VT, And, LR, CC1); in foldLogicOfSetCCs()
6013 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 && in foldLogicOfSetCCs()
6026 if (IsInteger && TLI.convertSetCCLogicToBitwiseLogic(OpVT) && CC0 == CC1 && in foldLogicOfSetCCs()
6030 if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) { in foldLogicOfSetCCs()
6035 return DAG.getSetCC(DL, VT, Or, Zero, CC1); in foldLogicOfSetCCs()
6039 if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) { in foldLogicOfSetCCs()
6066 CC1 = ISD::getSetCCSwappedOperands(CC1); in foldLogicOfSetCCs()
6073 ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, OpVT) in foldLogicOfSetCCs()
6074 : ISD::getSetCCOrOperation(CC0, CC1, OpVT); in foldLogicOfSetCCs()