Lines Matching defs:Reg

51 void RegScavenger::setRegUsed(Register Reg, LaneBitmask LaneMask) {
52   LiveUnits.addRegMasked(Reg, LaneMask);
65     SI.Reg = 0;
89       I.Reg = 0;
95 bool RegScavenger::isRegUsed(Register Reg, bool includeReserved) const {
96   if (isReserved(Reg))
98   return !LiveUnits.available(Reg);
102   for (Register Reg : *RC) {
103     if (!isRegUsed(Reg)) {
104       LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)
106       return Reg;
114   for (Register Reg : *RC)
115     if (!isRegUsed(Reg))
116       Mask.set(Reg);
152       for (MCPhysReg Reg : AllocationOrder) {
153         if (!MRI.isReserved(Reg) && Used.available(Reg) &&
154             LiveOut.available(Reg))
155           return std::make_pair(Reg, MBB.end());
177         for (MCPhysReg Reg : AllocationOrder) {
178           if (!MRI.isReserved(Reg) && Used.available(Reg)) {
179             AvilableReg = Reg;
223 RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
236     if (Scavenged[I].Reg != 0)
266   Scavenged[SI].Reg = Reg;
270   if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {
275                          TRI->getName(Reg) + " from class " +
280     TII->storeRegToStackSlot(*MBB, Before, Reg, true, FI, &RC, TRI, Register());
287     TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, TRI, Register());
308   MCPhysReg Reg = P.first;
311   if (Reg != 0 && SpillBefore == MBB.end()) {
312     LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)
314     return Reg;
320   assert(Reg != 0 && "No register left to scavenge!");
326   ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);
328   LiveUnits.removeReg(Reg);
329   LLVM_DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
331   return Reg;
412         Register Reg = MO.getReg();
416         if (!Reg.isVirtual() ||
417             Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
422         Register SReg = scavengeVReg(MRI, RS, Reg, true);
434       Register Reg = MO.getReg();
436       if (!Reg.isVirtual() ||
437           Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
448         Register SReg = scavengeVReg(MRI, RS, Reg, false);