260   ExtraInfo->LRE_DidCloneVirtReg(New, Old);  in LRE_DidCloneVirtReg()
290   auto Stage = ExtraInfo->getOrInitStage(Reg);  in enqueue()
293     ExtraInfo->setStage(Reg, Stage);  in enqueue()
487   unsigned Cascade = ExtraInfo->getOrAssignNewCascade(VirtReg.reg());  in evictInterference()
511     assert((ExtraInfo->getCascade(Intf->reg()) < Cascade ||  in evictInterference()
514     ExtraInfo->setCascade(Intf->reg(), Cascade);  in evictInterference()
1030     if (ExtraInfo->getOrInitStage(Reg.reg()) != RS_New)  in splitAroundRegion()
1036       ExtraInfo->setStage(Reg, RS_Spill);  in splitAroundRegion()
1047         ExtraInfo->setStage(Reg, RS_Split2);  in splitAroundRegion()
1242   if (ExtraInfo->getStage(VirtReg) >= RS_Split2)  in trySplitAroundHintReg()
1321     if (ExtraInfo->getOrInitStage(LI.reg()) == RS_New && IntvMap[I] == 0)  in tryBlockSplit()
1322       ExtraInfo->setStage(LI, RS_Spill);  in tryBlockSplit()
1476   ExtraInfo->setStage(LREdit.begin(), LREdit.end(), RS_Spill);  in tryInstructionSplit()
1645   bool ProgressRequired = ExtraInfo->getStage(VirtReg) >= RS_Split2;  in tryLocalSplit()
1781         ExtraInfo->setStage(LIS->getInterval(LREdit.get(I)), RS_Split2);  in tryLocalSplit()
1802   if (ExtraInfo->getStage(VirtReg) >= RS_Spill)  in trySplit()
1824   if (ExtraInfo->getStage(VirtReg) < RS_Split2) {  in trySplit()
1895       if (((ExtraInfo->getStage(*Intf) == RS_Done &&  in mayRecolorAllInterferences()
1968   assert((ExtraInfo->getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) &&  in tryLastChanceRecoloring()
2177   if (ExtraInfo->getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) {  in tryAssignCSRFirstTime()
2189   if (ExtraInfo->getStage(VirtReg) < RS_Split) {  in tryAssignCSRFirstTime()
2437   LiveRangeStage Stage = ExtraInfo->getStage(VirtReg);  in selectOrSplitImpl()
2439                     << ExtraInfo->getCascade(VirtReg.reg()) << '\n');  in selectOrSplitImpl()
2465     ExtraInfo->setStage(VirtReg, RS_Split);  in selectOrSplitImpl()
2489       ExtraInfo->getStage(VirtReg) < RS_Memory) {  in selectOrSplitImpl()
2494     ExtraInfo->setStage(VirtReg, RS_Memory);  in selectOrSplitImpl()
2502     ExtraInfo->setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);  in selectOrSplitImpl()
2749   ExtraInfo.emplace();  in runOnMachineFunction()