188   const TargetRegisterInfo *TRI = nullptr;  member in __anon43a0a7eb0111::RegAllocFastImpl
283     for (MCRegUnit Unit : TRI->regunits(PhysReg))  in markRegUsedInInstr()
298     for (MCRegUnit Unit : TRI->regunits(PhysReg))  in isRegUsedInInstr()
307     for (MCRegUnit Unit : TRI->regunits(PhysReg)) {  in markPhysRegUsedInInstr()
315     for (MCRegUnit Unit : TRI->regunits(PhysReg))  in unmarkRegUsedInInstr()
448   return ShouldAllocateRegisterImpl(*TRI, *MRI, Reg);  in shouldAllocateRegister()
452   for (MCRegUnit Unit : TRI->regunits(PhysReg))  in setPhysRegState()
457   for (MCRegUnit Unit : TRI->regunits(PhysReg)) {  in isPhysRegFree()
475   unsigned Size = TRI->getSpillSize(RC);  in getStackSpaceFor()
476   Align Alignment = TRI->getSpillAlign(RC);  in getStackSpaceFor()
584   LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) << " in "  in spill()
585                     << printReg(AssignedReg, TRI));  in spill()
590   TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI,  in spill()
644   LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into "  in reload()
645                     << printReg(PhysReg, TRI) << '\n');  in reload()
648   TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg);  in reload()
705     MCRegUnit FirstUnit = *TRI->regunits(PhysReg).begin();  in reloadAtBegin()
746   for (MCRegUnit Unit : TRI->regunits(PhysReg)) {  in displacePhysReg()
775   LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':');  in freePhysReg()
777   MCRegUnit FirstUnit = *TRI->regunits(PhysReg).begin();  in freePhysReg()
789     LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n');  in freePhysReg()
802   for (MCRegUnit Unit : TRI->regunits(PhysReg)) {  in calcSpillCost()
808                         << printReg(PhysReg, TRI) << '\n');  in calcSpillCost()
839       if (I->modifiesRegister(Reg, TRI) || --Limit == 0) {  in assignDanglingDebugValues()
861   LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to "  in assignVirtToPhysReg()
862                     << printReg(PhysReg, TRI) << '\n');  in assignVirtToPhysReg()
917                     << " in class " << TRI->getRegClassName(&RC)  in allocVirtReg()
918                     << " with hint " << printReg(Hint0, TRI) << '\n');  in allocVirtReg()
925       LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint0, TRI)  in allocVirtReg()
930       LLVM_DEBUG(dbgs() << "\tPreferred Register 0: " << printReg(Hint0, TRI)  in allocVirtReg()
943       LLVM_DEBUG(dbgs() << "\tPreferred Register 0: " << printReg(Hint1, TRI)  in allocVirtReg()
948       LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint1, TRI)  in allocVirtReg()
959     LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' ');  in allocVirtReg()
1024     PhysReg = TRI->getSubReg(PhysReg, SubRegIdx);  in allocVirtRegUndef()
1043       LLVM_DEBUG(dbgs() << "Need new assignment for " << printReg(PrevReg, TRI)  in defineLiveThroughVirtReg()
1050       LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to "  in defineLiveThroughVirtReg()
1051                         << printReg(PrevReg, TRI) << '\n');  in defineLiveThroughVirtReg()
1095     LLVM_DEBUG(dbgs() << "In def of " << printReg(VirtReg, TRI)  in defineVirtReg()
1097                       << printReg(LRI->PhysReg, TRI) << '\n');  in defineVirtReg()
1119                                      &RC, TRI, VirtReg);  in defineVirtReg()
1255   MO.setReg(TRI->getSubReg(PhysReg, MO.getSubReg()));  in setPhysReg()
1267     MI.addRegisterKilled(PhysReg, TRI, true);  in setPhysReg()
1276       MI.addRegisterDead(PhysReg, TRI, true);  in setPhysReg()
1278       MI.addRegisterDefined(PhysReg, TRI);  in setPhysReg()
1288   for (unsigned Unit = 1, UnitE = TRI->getNumRegUnits(); Unit != UnitE;  in dumpState()
1294       dbgs() << " " << printRegUnit(Unit, TRI) << "[P]";  in dumpState()
1299       dbgs() << ' ' << printRegUnit(Unit, TRI) << '=' << printReg(VirtReg);  in dumpState()
1310       assert(TRI->hasRegUnit(I->PhysReg, Unit) && "inverse mapping present");  in dumpState()
1323       for (MCRegUnit Unit : TRI->regunits(PhysReg)) {  in dumpState()
1334   assert(RegClassDefCounts.size() == TRI->getNumRegClasses());  in addRegClassDefCounts()
1340     for (unsigned RCIdx = 0, RCIdxEnd = TRI->getNumRegClasses();  in addRegClassDefCounts()
1342       const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx);  in addRegClassDefCounts()
1351   for (unsigned RCIdx = 0, RCIdxEnd = TRI->getNumRegClasses();  in addRegClassDefCounts()
1353     const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx);  in addRegClassDefCounts()
1354     for (MCRegAliasIterator Alias(Reg, TRI, true); Alias.isValid(); ++Alias) {  in addRegClassDefCounts()
1377         LLVM_DEBUG(dbgs() << "mark extra used: " << printReg(Reg, TRI) << '\n');  in findAndSortDefOperandIndexes()
1396   SmallVector<unsigned> RegClassDefCounts(TRI->getNumRegClasses(), 0);  in findAndSortDefOperandIndexes()
1692       if (MI.readsRegister(Reg, TRI))  in allocateInstruction()
1776   RegUnitStates.assign(TRI->getNumRegUnits(), regFree);  in allocateBasicBlock()
1837   TRI = STI.getRegisterInfo();  in runOnMachineFunction()
1842   unsigned NumRegUnits = TRI->getNumRegUnits();  in runOnMachineFunction()