Lines Matching refs:MO
362 void allocVirtRegUndef(MachineOperand &MO);
369 bool useVirtReg(MachineInstr &MI, MachineOperand &MO, Register VirtReg);
376 bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
585 for (MachineOperand *MO : LRIDbgOperands) in spill()
586 SpilledOperandsMap[MO->getParent()].push_back(MO); in spill()
612 MachineOperand &MO = DBG.getDebugOperand(0); in spill() local
613 if (MO.isReg() && MO.getReg() == 0) { in spill()
654 for (MachineOperand &MO : I->operands()) { in getMBBBeginInsertionPoint()
655 if (MO.isReg()) in getMBBBeginInsertionPoint()
656 PrologLiveIns.insert(MO.getReg()); in getMBBBeginInsertionPoint()
827 for (MachineOperand &MO : DbgValue->getDebugOperandsForReg(VirtReg)) { in assignDanglingDebugValues()
828 MO.setReg(SetToReg); in assignDanglingDebugValues()
830 MO.setIsRenamable(); in assignDanglingDebugValues()
980 void RegAllocFastImpl::allocVirtRegUndef(MachineOperand &MO) { in allocVirtRegUndef() argument
981 assert(MO.isUndef() && "expected undef use"); in allocVirtRegUndef()
982 Register VirtReg = MO.getReg(); in allocVirtRegUndef()
998 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef()
1001 MO.setSubReg(0); in allocVirtRegUndef()
1003 MO.setReg(PhysReg); in allocVirtRegUndef()
1004 MO.setIsRenamable(true); in allocVirtRegUndef()
1032 MachineOperand &MO = MI.getOperand(OpNum); in defineLiveThroughVirtReg() local
1033 if (MO.getSubReg() && !MO.isUndef()) { in defineLiveThroughVirtReg()
1052 MachineOperand &MO = MI.getOperand(OpNum); in defineVirtReg() local
1057 if (!MO.isDead()) { in defineVirtReg()
1062 MO.setIsDead(true); in defineVirtReg()
1074 return setPhysReg(MI, MO, MCRegister::NoRegister); in defineVirtReg()
1075 return setPhysReg(MI, MO, *AllocationOrder.begin()); in defineVirtReg()
1100 for (MachineOperand &MO : MI.operands()) { in defineVirtReg()
1101 if (MO.isMBB()) { in defineVirtReg()
1102 MachineBasicBlock *Succ = MO.getMBB(); in defineVirtReg()
1120 return setPhysReg(MI, MO, PhysReg); in defineVirtReg()
1125 bool RegAllocFastImpl::useVirtReg(MachineInstr &MI, MachineOperand &MO, in useVirtReg() argument
1134 if (!MO.isKill()) { in useVirtReg()
1139 MO.setIsKill(true); in useVirtReg()
1143 assert((!MO.isKill() || LRI->LastUse == &MI) && "Invalid kill flag"); in useVirtReg()
1148 assert(!MO.isTied() && "tied op should be allocated"); in useVirtReg()
1165 return setPhysReg(MI, MO, MCRegister::NoRegister); in useVirtReg()
1166 return setPhysReg(MI, MO, *AllocationOrder.begin()); in useVirtReg()
1176 return setPhysReg(MI, MO, LRI->PhysReg); in useVirtReg()
1181 bool RegAllocFastImpl::setPhysReg(MachineInstr &MI, MachineOperand &MO, in setPhysReg() argument
1183 if (!MO.getSubReg()) { in setPhysReg()
1184 MO.setReg(PhysReg); in setPhysReg()
1185 MO.setIsRenamable(true); in setPhysReg()
1190 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister()); in setPhysReg()
1191 MO.setIsRenamable(true); in setPhysReg()
1195 if (!MO.isDef()) in setPhysReg()
1196 MO.setSubReg(0); in setPhysReg()
1200 if (MO.isKill()) { in setPhysReg()
1208 if (MO.isDef() && MO.isUndef()) { in setPhysReg()
1209 if (MO.isDead()) in setPhysReg()
1305 const MachineOperand &MO = MI.getOperand(I); in findAndSortDefOperandIndexes() local
1306 if (!MO.isReg()) in findAndSortDefOperandIndexes()
1308 Register Reg = MO.getReg(); in findAndSortDefOperandIndexes()
1309 if (MO.readsReg()) { in findAndSortDefOperandIndexes()
1316 if (MO.isDef() && Reg.isVirtual() && shouldAllocateRegister(Reg)) in findAndSortDefOperandIndexes()
1332 for (const MachineOperand &MO : MI.operands()) in findAndSortDefOperandIndexes() local
1333 if (MO.isReg() && MO.isDef()) in findAndSortDefOperandIndexes()
1334 addRegClassDefCounts(RegClassDefCounts, MO.getReg()); in findAndSortDefOperandIndexes()
1373 static bool isTiedToNotUndef(const MachineOperand &MO) { in isTiedToNotUndef() argument
1374 if (!MO.isTied()) in isTiedToNotUndef()
1376 const MachineInstr &MI = *MO.getParent(); in isTiedToNotUndef()
1377 unsigned TiedIdx = MI.findTiedOperandIdx(MI.getOperandNo(&MO)); in isTiedToNotUndef()
1411 for (MachineOperand &MO : MI.operands()) { in allocateInstruction()
1412 if (MO.isReg()) { in allocateInstruction()
1413 Register Reg = MO.getReg(); in allocateInstruction()
1417 if (MO.isDef()) { in allocateInstruction()
1420 if (MO.isEarlyClobber()) { in allocateInstruction()
1424 if (isTiedToNotUndef(MO) || (MO.getSubReg() != 0 && !MO.isUndef())) in allocateInstruction()
1429 if (MO.isDef()) { in allocateInstruction()
1432 if (MO.isEarlyClobber()) in allocateInstruction()
1435 MO.setIsDead(true); in allocateInstruction()
1437 if (MO.readsReg()) in allocateInstruction()
1441 } else if (MO.isRegMask()) { in allocateInstruction()
1443 RegMasks.push_back(MO.getRegMask()); in allocateInstruction()
1465 MachineOperand &MO = MI.getOperand(OpIdx); in allocateInstruction() local
1466 LLVM_DEBUG(dbgs() << "Allocating " << MO << '\n'); in allocateInstruction()
1467 Register Reg = MO.getReg(); in allocateInstruction()
1468 if (MO.isEarlyClobber() || isTiedToNotUndef(MO) || in allocateInstruction()
1469 (MO.getSubReg() && !MO.isUndef())) { in allocateInstruction()
1484 for (MachineOperand &MO : MI.operands()) { in allocateInstruction()
1485 if (!MO.isReg() || !MO.isDef()) in allocateInstruction()
1487 Register Reg = MO.getReg(); in allocateInstruction()
1490 defineVirtReg(MI, MI.getOperandNo(&MO), Reg); in allocateInstruction()
1502 for (MachineOperand &MO : reverse(MI.operands())) { in allocateInstruction()
1503 if (!MO.isReg() || !MO.isDef()) in allocateInstruction()
1506 Register Reg = MO.getReg(); in allocateInstruction()
1510 if (Reg.isPhysical() && MO.getSubReg() != 0) { in allocateInstruction()
1511 MO.setSubReg(0); in allocateInstruction()
1515 assert((!MO.isTied() || !isClobberedByRegMasks(MO.getReg())) && in allocateInstruction()
1519 if (isTiedToNotUndef(MO) || MO.isEarlyClobber()) in allocateInstruction()
1552 for (MachineOperand &MO : MI.operands()) { in allocateInstruction()
1553 if (!MO.isReg() || !MO.readsReg()) in allocateInstruction()
1555 Register Reg = MO.getReg(); in allocateInstruction()
1561 MO.setIsKill(true); in allocateInstruction()
1572 for (MachineOperand &MO : MI.operands()) { in allocateInstruction()
1573 if (!MO.isReg() || !MO.isUse()) in allocateInstruction()
1575 Register Reg = MO.getReg(); in allocateInstruction()
1579 if (MO.isUndef()) { in allocateInstruction()
1588 assert(!MO.isInternalRead() && "Bundles not supported"); in allocateInstruction()
1589 assert(MO.readsReg() && "reading use"); in allocateInstruction()
1590 ReArrangedImplicitMOs = useVirtReg(MI, MO, Reg); in allocateInstruction()
1600 for (MachineOperand &MO : MI.all_uses()) { in allocateInstruction()
1601 Register Reg = MO.getReg(); in allocateInstruction()
1605 assert(MO.isUndef() && "Should only have undef virtreg uses left"); in allocateInstruction()
1606 allocVirtRegUndef(MO); in allocateInstruction()
1612 for (MachineOperand &MO : reverse(MI.all_defs())) { in allocateInstruction()
1613 if (!MO.isEarlyClobber()) in allocateInstruction()
1615 assert(!MO.getSubReg() && "should be already handled in def processing"); in allocateInstruction()
1617 Register Reg = MO.getReg(); in allocateInstruction()
1651 for (const auto &MO : MI.debug_operands()) { in handleDebugValue() local
1652 if (!MO.isReg()) in handleDebugValue()
1654 Register Reg = MO.getReg(); in handleDebugValue()
1694 for (MachineOperand &MO : BundledMI->operands()) { in handleBundle()
1695 if (!MO.isReg()) in handleBundle()
1698 Register Reg = MO.getReg(); in handleBundle()
1706 setPhysReg(MI, MO, DI->second); in handleBundle()