Lines Matching full:rr
126 std::set<RegisterId> PhysicalRegisterInfo::getUnits(RegisterRef RR) const {
129 if (RR.Reg == 0)
132 if (RR.isReg()) {
133 if (RR.Mask.none())
135 for (MCRegUnitMaskIterator UM(RR.idx(), &TRI); UM.isValid(); ++UM) {
137 if ((M & RR.Mask).any())
143 assert(RR.isMask());
145 const uint32_t *MB = getRegMaskBits(RR.idx());
165 RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, unsigned R) const {
166 if (RR.Reg == R)
167 return RR;
168 if (unsigned Idx = TRI.getSubRegIndex(R, RR.Reg))
169 return RegisterRef(R, TRI.composeSubRegIndexLaneMask(Idx, RR.Mask));
170 if (unsigned Idx = TRI.getSubRegIndex(RR.Reg, R)) {
174 LaneBitmask M = TRI.reverseComposeSubRegIndexLaneMask(Idx, RR.Mask);
279 bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
280 if (RR.isMask())
281 return Units.anyCommon(PRI.getMaskUnits(RR.Reg));
283 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
285 if ((P.second & RR.Mask).any())
292 bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
293 if (RR.isMask()) {
294 BitVector T(PRI.getMaskUnits(RR.Reg));
298 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
300 if ((P.second & RR.Mask).any())
307 RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
308 if (RR.isMask()) {
309 Units |= PRI.getMaskUnits(RR.Reg);
313 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
315 if ((P.second & RR.Mask).any())
326 RegisterAggr &RegisterAggr::intersect(RegisterRef RR) {
327 return intersect(RegisterAggr(PRI).insert(RR));
335 RegisterAggr &RegisterAggr::clear(RegisterRef RR) {
336 return clear(RegisterAggr(PRI).insert(RR));
344 RegisterRef RegisterAggr::intersectWith(RegisterRef RR) const {
346 T.insert(RR).intersect(*this);
354 RegisterRef RegisterAggr::clearIn(RegisterRef RR) const {
355 return RegisterAggr(PRI).insert(RR).clear(*this).makeRegRef();