Lines Matching +full:saw +full:- +full:reg
1 //===- PeepholeOptimizer.cpp - Peephole Optimizations ---------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 // - Optimize Extensions
18 // will replace some uses of the pre-extension value with uses of the
19 // sub-register of the results.
21 // - Optimize Comparisons
42 // - Optimize Loads:
48 // - Optimize Copies and Bitcast (more generally, target specific copies):
54 // b = copy A <-- cross-bank copy
55 // C = copy b <-- cross-bank copy
57 // b = copy A <-- cross-bank copy
58 // C = copy A <-- same-bank copy
61 // b = bitcast A <-- cross-bank copy
62 // C = bitcast b <-- cross-bank copy
64 // b = bitcast A <-- cross-bank copy
65 // C = copy A <-- same-bank copy
66 //===----------------------------------------------------------------------===//
102 #define DEBUG_TYPE "peephole-opt"
106 Aggressive("aggressive-ext-opt", cl::Hidden,
110 DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
117 DisableAdvCopyOpt("disable-adv-copy-opt", cl::Hidden, cl::init(false),
121 "disable-non-allocatable-phys-copy-opt", cl::Hidden, cl::init(false),
122 cl::desc("Disable non-allocatable physical register copy optimization"));
127 "rewrite-phi-limit", cl::Hidden, cl::init(10),
133 "recurrence-chain-limit", cl::Hidden, cl::init(3),
145 STATISTIC(NumNAPhysCopies, "Number of non-allocatable physical copies removed");
185 /// Track Def -> Use info used for rewriting copies.
213 bool findTargetRecurrence(Register Reg,
224 /// Is the register \p Reg a non-allocatable physical register?
225 bool isNAPhysCopy(Register Reg);
227 /// If copy instruction \p MI is a non-allocatable virtual<->physical
229 /// non-allocatable physical register was previously copied to a virtual
230 /// registered and hasn't been clobbered, the virt->phys copy can be
275 if (!SrcReg.isVirtual() && !MRI->isConstantPhysReg(SrcReg)) in getCopySrc()
290 if (It != CopySrcMIs.end() && It->second == &MI) in deleteChangedCopy()
340 ValueTrackerResult(Register Reg, unsigned SubReg) { in ValueTrackerResult() argument
341 addSource(Reg, SubReg); in ValueTrackerResult()
359 assert(Idx < getNumSources() && "Reg pair source out of index"); in setSource()
370 assert(Idx < getNumSources() && "Reg source out of index"); in getSrcReg()
371 return RegSrcs[Idx].Reg; in getSrcReg()
397 /// follows the use-def chain to find successive suitable sources.
412 /// The current point into the use-def chain.
422 Register Reg; member in __anon776574090111::ValueTracker
455 /// Create a ValueTracker instance for the value defined by \p Reg.
458 /// definition of \p Reg.
459 /// If \p Reg is a physical register, a value tracker constructed with
461 /// Indeed, when \p Reg is a physical register that constructor does not
462 /// know which definition of \p Reg it should track.
464 ValueTracker(Register Reg, unsigned DefSubReg, in ValueTracker() argument
467 : DefSubReg(DefSubReg), Reg(Reg), MRI(MRI), TII(TII) { in ValueTracker()
468 if (!Reg.isPhysical()) { in ValueTracker()
469 Def = MRI.getVRegDef(Reg); in ValueTracker()
470 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
474 /// Following the use-def chain, get the next available source
495 /// If instruction is a copy-like instruction, i.e. it reads a single register in INITIALIZE_PASS_DEPENDENCY()
497 /// source value is preserved as a sub-register of the result, then replace all in INITIALIZE_PASS_DEPENDENCY()
508 if (!TII->isCoalescableExtInstr(MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
514 if (MRI->hasOneNonDBGUse(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
519 // sub-registers. Don't change the class until we commit. in INITIALIZE_PASS_DEPENDENCY()
520 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
521 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
525 // The ext instr may be operating on a sub-register of SrcReg as well. in INITIALIZE_PASS_DEPENDENCY()
526 // PPC::EXTSW is a 32 -> 64-bit sign extension, but it reads a 64-bit in INITIALIZE_PASS_DEPENDENCY()
531 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
536 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg)) in INITIALIZE_PASS_DEPENDENCY()
546 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) { in INITIALIZE_PASS_DEPENDENCY()
551 if (UseMI->isPHI()) { in INITIALIZE_PASS_DEPENDENCY()
577 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) in INITIALIZE_PASS_DEPENDENCY()
580 MachineBasicBlock *UseMBB = UseMI->getParent(); in INITIALIZE_PASS_DEPENDENCY()
586 // Non-local uses where the result of the extension is used. Always in INITIALIZE_PASS_DEPENDENCY()
589 } else if (Aggressive && DT->dominates(&MBB, UseMBB)) { in INITIALIZE_PASS_DEPENDENCY()
613 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg)) in INITIALIZE_PASS_DEPENDENCY()
617 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
619 MachineInstr *UseMI = UseMO->getParent(); in INITIALIZE_PASS_DEPENDENCY()
620 MachineBasicBlock *UseMBB = UseMI->getParent(); in INITIALIZE_PASS_DEPENDENCY()
626 MRI->clearKillFlags(DstReg); in INITIALIZE_PASS_DEPENDENCY()
627 MRI->constrainRegClass(DstReg, DstRC); in INITIALIZE_PASS_DEPENDENCY()
645 RC = MRI->getRegClass(UseMI->getOperand(0).getReg()); in INITIALIZE_PASS_DEPENDENCY()
647 Register NewVR = MRI->createVirtualRegister(RC); in INITIALIZE_PASS_DEPENDENCY()
648 BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(), in INITIALIZE_PASS_DEPENDENCY()
649 TII->get(TargetOpcode::COPY), NewVR) in INITIALIZE_PASS_DEPENDENCY()
652 UseMO->setSubReg(0); in INITIALIZE_PASS_DEPENDENCY()
654 UseMO->setReg(NewVR); in INITIALIZE_PASS_DEPENDENCY()
672 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
678 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { in optimizeCmpInstr()
679 LLVM_DEBUG(dbgs() << " -> Successfully optimized compare!\n"); in optimizeCmpInstr()
694 if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable)) in optimizeSelect()
698 if (!TII->optimizeSelect(MI, LocalMIs)) in optimizeSelect()
708 return TII->optimizeCondBranch(MI); in optimizeCondBranch()
712 /// for the value defined by \p Reg and \p SubReg.
714 /// retrieve all Def -> Use along the way up to the next source. Any found
719 /// share the same register file as \p Reg and \p SubReg. The client should
728 Register Reg = RegSubReg.Reg; in findNextSource() local
729 if (Reg.isPhysical()) in findNextSource()
731 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource()
741 if (CurSrcPair.Reg.isPhysical()) in findNextSource()
744 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII); in findNextSource()
754 // Insert the Def -> Use entry for the recently found source. in findNextSource()
785 // Do not extend the live-ranges of physical registers as they add in findNextSource()
787 // the live-range of a physical register, unlike SSA virtual register, in findNextSource()
789 if (CurSrcPair.Reg.isPhysical()) in findNextSource()
793 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg); in findNextSource()
794 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
809 return CurSrcPair.Reg != Reg; in findNextSource()
823 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
834 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
836 // Since we're extended the lifetime of RegPair.Reg, clear the in insertPHI()
837 // kill flags to account for that and make RegPair.Reg reaches in insertPHI()
839 MRI.clearKillFlags(RegPair.Reg); in insertPHI()
861 /// coalescer friendly. In other words, given a copy-like instruction
937 /// rewrite a uncoalescable copy-like instruction. This method return
941 // Find the next non-dead definition and continue from there. in getNextRewritableSource()
997 // Bail if we have to compose sub-register indices. in getNextRewritableSource()
1007 // We are rewriting the inserted reg. in RewriteCurrentSource()
1038 // If we have to compose sub-register indices, bail out. in getNextRewritableSource()
1064 CurrentSrcIdx = -1; in RewriteCurrentSource()
1066 // Get rid of the sub-register index. in RewriteCurrentSource()
1114 Src.Reg = MOInsertedReg.getReg(); in getNextRewritableSource()
1115 // If we have to compose sub-register indices, bail out. in getNextRewritableSource()
1124 Dst.Reg = MODef.getReg(); in getNextRewritableSource()
1125 // If we have to compose sub-registers, bail. in getNextRewritableSource()
1148 // Handle uncoalescable copy-like instructions. in getCopyRewriter()
1167 /// Given a \p Def.Reg and Def.SubReg pair, use \p RewriteMap to find
1178 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
1188 LookupSrc.Reg = Res.getSrcReg(0); in getNewSource()
1209 LLVM_DEBUG(dbgs() << "-- getNewSource\n"); in getNewSource()
1248 while (CpyRewriter->getNextRewritableSource(Src, TrackPair)) { in optimizeCoalescableCopy()
1260 if (Src.Reg == NewSrc.Reg || NewSrc.Reg == 0) in optimizeCoalescableCopy()
1264 if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) { in optimizeCoalescableCopy()
1265 // We may have extended the live-range of NewSrc, account for that. in optimizeCoalescableCopy()
1266 MRI->clearKillFlags(NewSrc.Reg); in optimizeCoalescableCopy()
1270 // TODO: We could have a clean-up method to tidy the instruction. in optimizeCoalescableCopy()
1287 assert(!Def.Reg.isPhysical() && "We do not rewrite physical registers"); in rewriteSource()
1293 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource()
1294 Register NewVReg = MRI->createVirtualRegister(DefRC); in rewriteSource()
1298 TII->get(TargetOpcode::COPY), NewVReg) in rewriteSource()
1299 .addReg(NewSrc.Reg, 0, NewSrc.SubReg); in rewriteSource()
1302 NewCopy->getOperand(0).setSubReg(Def.SubReg); in rewriteSource()
1303 NewCopy->getOperand(0).setIsUndef(); in rewriteSource()
1306 LLVM_DEBUG(dbgs() << "-- RewriteSource\n"); in rewriteSource()
1309 MRI->replaceRegWith(Def.Reg, NewVReg); in rewriteSource()
1310 MRI->clearKillFlags(NewVReg); in rewriteSource()
1312 // We extended the lifetime of NewSrc.Reg, clear the kill flags to in rewriteSource()
1314 MRI->clearKillFlags(NewSrc.Reg); in rewriteSource()
1319 /// Optimize copy-like instructions to create
1321 /// The optimization tries to kill-off the \p MI by looking
1345 if (Def.Reg.isPhysical()) in optimizeUncoalescableCopy()
1381 Register Reg = MI.getOperand(0).getReg(); in isLoadFoldable() local
1382 // To reduce compilation time, we check MRI->hasOneNonDBGUser when inserting in isLoadFoldable()
1385 if (Reg.isVirtual() && !MI.getOperand(0).getSubReg() && in isLoadFoldable()
1386 MRI->hasOneNonDBGUser(Reg)) { in isLoadFoldable()
1387 FoldAsLoadDefCandidates.insert(Reg); in isLoadFoldable()
1399 Register Reg = MI.getOperand(0).getReg(); in isMoveImmediate() local
1400 if (!Reg.isVirtual()) in isMoveImmediate()
1404 if (!MI.isMoveImmediate() && !TII->getConstValDefinedInReg(MI, Reg, ImmVal)) in isMoveImmediate()
1407 ImmDefMIs.insert(std::make_pair(Reg, &MI)); in isMoveImmediate()
1408 ImmDefRegs.insert(Reg); in isMoveImmediate()
1423 Register Reg = MO.getReg(); in foldImmediate() local
1424 if (!Reg.isVirtual()) in foldImmediate()
1426 if (ImmDefRegs.count(Reg) == 0) in foldImmediate()
1428 DenseMap<Register, MachineInstr *>::iterator II = ImmDefMIs.find(Reg); in foldImmediate()
1430 if (TII->foldImmediate(MI, *II->second, Reg, MRI)) { in foldImmediate()
1435 if (MRI->getVRegDef(Reg) && in foldImmediate()
1436 MI.isIdenticalTo(*II->second, MachineInstr::IgnoreVRegDefs)) { in foldImmediate()
1439 MRI->getRegClass(DstReg) == MRI->getRegClass(Reg)) { in foldImmediate()
1440 MRI->replaceRegWith(DstReg, Reg); in foldImmediate()
1477 // First copy of this reg seen. in foldRedundantCopy()
1481 MachineInstr *PrevCopy = CopySrcMIs.find(SrcPair)->second; in foldRedundantCopy()
1483 assert(SrcPair.SubReg == PrevCopy->getOperand(1).getSubReg() && in foldRedundantCopy()
1486 Register PrevDstReg = PrevCopy->getOperand(0).getReg(); in foldRedundantCopy()
1492 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg)) in foldRedundantCopy()
1495 MRI->replaceRegWith(DstReg, PrevDstReg); in foldRedundantCopy()
1498 MRI->clearKillFlags(PrevDstReg); in foldRedundantCopy()
1502 bool PeepholeOptimizer::isNAPhysCopy(Register Reg) { in isNAPhysCopy() argument
1503 return Reg.isPhysical() && !MRI->isAllocatable(Reg); in isNAPhysCopy()
1517 // Avoid using a datastructure which can track multiple live non-allocatable in foldRedundantNAPhysCopy()
1518 // phys->virt copies since LLVM doesn't seem to do this. in foldRedundantNAPhysCopy()
1530 // non-allocatable physical register after the copy to virtual. in foldRedundantNAPhysCopy()
1536 Register PrevDstReg = PrevCopy->second->getOperand(0).getReg(); in foldRedundantNAPhysCopy()
1538 // Remove the virt->phys copy: we saw the virtual register definition, and in foldRedundantNAPhysCopy()
1539 // the non-allocatable physical register's state hasn't changed since then. in foldRedundantNAPhysCopy()
1545 // Potential missed optimization opportunity: we saw a different virtual in foldRedundantNAPhysCopy()
1546 // register get a copy of the non-allocatable physical register, and we only in foldRedundantNAPhysCopy()
1547 // track one such copy. Avoid getting confused by this new non-allocatable in foldRedundantNAPhysCopy()
1560 Register Reg, const SmallSet<Register, 2> &TargetRegs, in findTargetRecurrence() argument
1562 // Recurrence found if Reg is in TargetRegs. in findTargetRecurrence()
1563 if (TargetRegs.count(Reg)) in findTargetRecurrence()
1571 if (!MRI->hasOneNonDBGUse(Reg)) in findTargetRecurrence()
1578 MachineInstr &MI = *(MRI->use_instr_nodbg_begin(Reg)); in findTargetRecurrence()
1579 unsigned Idx = MI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr); in findTargetRecurrence()
1603 if (TII->findCommutedOpIndices(MI, Idx, CommIdx) && CommIdx == TiedUseIdx) { in findTargetRecurrence()
1649 TII->commuteInstruction(*(RI.getMI()), false, (*CP).first, in optimizeRecurrence()
1693 // Track when a non-allocatable physical register is copied to a virtual in runOnMachineFunction()
1697 // without any intervening re-definition of $physreg. in runOnMachineFunction()
1702 bool IsLoopHeader = MLI->isLoopHeader(&MBB); in runOnMachineFunction()
1713 if (MI->isDebugInstr()) in runOnMachineFunction()
1716 if (MI->isPosition()) in runOnMachineFunction()
1719 if (IsLoopHeader && MI->isPHI()) { in runOnMachineFunction()
1726 if (!MI->isCopy()) { in runOnMachineFunction()
1727 for (const MachineOperand &MO : MI->operands()) { in runOnMachineFunction()
1730 Register Reg = MO.getReg(); in runOnMachineFunction() local
1731 if (MO.isDef() && isNAPhysCopy(Reg)) { in runOnMachineFunction()
1732 const auto &Def = NAPhysToVirtMIs.find(Reg); in runOnMachineFunction()
1734 // A new definition of the non-allocatable physical register in runOnMachineFunction()
1755 if (MI->isImplicitDef() || MI->isKill()) in runOnMachineFunction()
1758 if (MI->isInlineAsm() || MI->hasUnmodeledSideEffects()) { in runOnMachineFunction()
1759 // Blow away all non-allocatable physical registers knowledge since we in runOnMachineFunction()
1770 (MI->isCompare() && optimizeCmpInstr(*MI)) || in runOnMachineFunction()
1771 (MI->isSelect() && optimizeSelect(*MI, LocalMIs))) { in runOnMachineFunction()
1778 if (MI->isConditionalBranch() && optimizeCondBranch(*MI)) { in runOnMachineFunction()
1789 if (MI->isCopy() && (foldRedundantCopy(*MI) || in runOnMachineFunction()
1793 MI->eraseFromParent(); in runOnMachineFunction()
1828 const MCInstrDesc &MIDesc = MI->getDesc(); in runOnMachineFunction()
1829 for (unsigned i = MIDesc.getNumDefs(); i != MI->getNumOperands(); in runOnMachineFunction()
1831 const MachineOperand &MOp = MI->getOperand(i); in runOnMachineFunction()
1843 TII->optimizeLoadInstr(*MI, MRI, FoldAsLoadDefReg, DefMI)) { in runOnMachineFunction()
1852 if (MI->shouldUpdateCallSiteInfo()) in runOnMachineFunction()
1853 MI->getMF()->moveCallSiteInfo(MI, FoldMI); in runOnMachineFunction()
1854 MI->eraseFromParent(); in runOnMachineFunction()
1855 DefMI->eraseFromParent(); in runOnMachineFunction()
1856 MRI->markUsesInDebugValueAsUndef(FoldedReg); in runOnMachineFunction()
1871 if (MI->isLoadFoldBarrier()) { in runOnMachineFunction()
1883 assert(Def->isCopy() && "Invalid definition"); in getNextSourceFromCopy()
1888 assert(Def->getNumOperands() - Def->getNumImplicitOperands() == 2 && in getNextSourceFromCopy()
1890 assert(!Def->hasImplicitDef() && "Only implicit uses are allowed"); in getNextSourceFromCopy()
1892 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1897 const MachineOperand &Src = Def->getOperand(1); in getNextSourceFromCopy()
1904 assert(Def->isBitcast() && "Invalid definition"); in getNextSourceFromBitcast()
1907 if (Def->mayRaiseFPException() || Def->hasUnmodeledSideEffects()) in getNextSourceFromBitcast()
1911 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
1913 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1919 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast()
1922 const MachineOperand &MO = Def->getOperand(OpIdx); in getNextSourceFromBitcast()
1937 if (SrcIdx >= Def->getNumOperands()) in getNextSourceFromBitcast()
1947 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
1954 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()
1957 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
1980 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs)) in getNextSourceFromRegSequence()
1988 return ValueTrackerResult(RegSeqInput.Reg, RegSeqInput.SubReg); in getNextSourceFromRegSequence()
1991 // If the subreg we are tracking is super-defined by another subreg, in getNextSourceFromRegSequence()
1998 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && in getNextSourceFromInsertSubreg()
2001 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
2014 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg)) in getNextSourceFromInsertSubreg()
2025 return ValueTrackerResult(InsertedReg.Reg, InsertedReg.SubReg); in getNextSourceFromInsertSubreg()
2030 const MachineOperand &MODef = Def->getOperand(DefIdx); in getNextSourceFromInsertSubreg()
2034 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) || in getNextSourceFromInsertSubreg()
2038 // Get the TRI and check if the inserted sub-register overlaps with the in getNextSourceFromInsertSubreg()
2039 // sub-register we are tracking. in getNextSourceFromInsertSubreg()
2042 !(TRI->getSubRegIndexLaneMask(DefSubReg) & in getNextSourceFromInsertSubreg()
2043 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)).none()) in getNextSourceFromInsertSubreg()
2047 return ValueTrackerResult(BaseReg.Reg, DefSubReg); in getNextSourceFromInsertSubreg()
2051 assert((Def->isExtractSubreg() || in getNextSourceFromExtractSubreg()
2052 Def->isExtractSubregLike()) && "Invalid definition"); in getNextSourceFromExtractSubreg()
2067 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg)) in getNextSourceFromExtractSubreg()
2075 return ValueTrackerResult(ExtractSubregInputReg.Reg, in getNextSourceFromExtractSubreg()
2080 assert(Def->isSubregToReg() && "Invalid definition"); in getNextSourceFromSubregToReg()
2088 if (DefSubReg != Def->getOperand(3).getImm()) in getNextSourceFromSubregToReg()
2092 if (Def->getOperand(2).getSubReg()) in getNextSourceFromSubregToReg()
2095 return ValueTrackerResult(Def->getOperand(2).getReg(), in getNextSourceFromSubregToReg()
2096 Def->getOperand(3).getImm()); in getNextSourceFromSubregToReg()
2101 assert(Def->isPHI() && "Invalid definition"); in getNextSourceFromPHI()
2106 if (Def->getOperand(0).getSubReg() != DefSubReg) in getNextSourceFromPHI()
2110 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) { in getNextSourceFromPHI()
2111 const MachineOperand &MO = Def->getOperand(i); in getNextSourceFromPHI()
2126 assert(((Def->getOperand(DefIdx).isDef() && in getNextSourceImpl()
2127 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
2128 Def->getDesc().isVariadic())) || in getNextSourceImpl()
2129 Def->getOperand(DefIdx).isImplicit()) && in getNextSourceImpl()
2131 if (Def->isCopy()) in getNextSourceImpl()
2133 if (Def->isBitcast()) in getNextSourceImpl()
2139 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
2141 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) in getNextSourceImpl()
2143 if (Def->isExtractSubreg() || Def->isExtractSubregLike()) in getNextSourceImpl()
2145 if (Def->isSubregToReg()) in getNextSourceImpl()
2147 if (Def->isPHI()) in getNextSourceImpl()
2153 // If we reach a point where we cannot move up in the use-def chain, in getNextSource()
2165 Reg = Res.getSrcReg(0); in getNextSource()
2166 // Update the result before moving up in the use-def chain in getNextSource()
2170 // If we can still move up in the use-def chain, move to the next in getNextSource()
2172 if (!Reg.isPhysical() && OneRegSrc) { in getNextSource()
2173 MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg); in getNextSource()
2175 Def = DI->getParent(); in getNextSource()
2186 // early by cutting the use-def chain. in getNextSource()