Lines Matching +full:straight +full:- +full:forward
1 //===- MachineSink.cpp - Sinking for machine instructions -----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 // for an LLVM-IR-level sinking pass. It is only designed to sink simple
16 //===----------------------------------------------------------------------===//
65 #define DEBUG_TYPE "machine-sink"
68 SplitEdges("machine-sink-split",
73 UseBlockFreqInfo("machine-sink-bfi",
78 "machine-sink-split-probability-threshold",
80 "Percentage threshold for splitting single-instruction critical edge. "
87 "machine-sink-load-instrs-threshold",
88 cl::desc("Do not try to find alias store for a load if there is a in-path "
93 "machine-sink-load-blocks-threshold",
95 "the straight line is higher than this threshold."),
99 SinkInstsIntoCycle("sink-insts-to-avoid-spills",
105 "machine-sink-cycle-limit",
135 // {register to sink, sink-to block} -> the first sink-from block.
136 // We're recording the first sink-from block because that (critical) edge
152 /// post-dominated by another DBG_VALUE of the same variable location.
159 /// would re-order assignments.
244 /// This is easily rectified by forwarding the non-dominated debug uses
302 for (MachineBasicBlock::const_iterator PI = BB->getFirstNonPHI(); PI != End; in INITIALIZE_PASS_DEPENDENCY()
305 if (!TII->isBasicBlockPrologue(*PI)) in INITIALIZE_PASS_DEPENDENCY()
315 (TII->isIgnorableUse(MO) || (MRI && MRI->isConstantPhysReg(Reg)))) in INITIALIZE_PASS_DEPENDENCY()
317 if (PI->modifiesRegister(Reg, TRI)) in INITIALIZE_PASS_DEPENDENCY()
320 if (PI->readsRegister(Reg, TRI)) in INITIALIZE_PASS_DEPENDENCY()
322 // Check for interference with non-dead defs in INITIALIZE_PASS_DEPENDENCY()
323 auto *DefOp = PI->findRegisterDefOperand(Reg, TRI, false, true); in INITIALIZE_PASS_DEPENDENCY()
324 if (DefOp && !DefOp->isDead()) in INITIALIZE_PASS_DEPENDENCY()
341 !MRI->hasOneNonDBGUse(SrcReg)) in PerformTrivialForwardCoalescing()
344 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); in PerformTrivialForwardCoalescing()
345 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in PerformTrivialForwardCoalescing()
349 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in PerformTrivialForwardCoalescing()
350 if (DefMI->isCopyLike()) in PerformTrivialForwardCoalescing()
354 MRI->replaceRegWith(DstReg, SrcReg); in PerformTrivialForwardCoalescing()
359 MRI->clearKillFlags(SrcReg); in PerformTrivialForwardCoalescing()
372 if (!TII->shouldSink(MI)) in PerformSinkAndFold()
380 // Convergent operations may not be made control-dependent on additional in PerformSinkAndFold()
387 // Don't sink more than two register uses - it'll cover most of the cases and in PerformSinkAndFold()
421 (MRI->isConstantPhysReg(Reg) || TII->isIgnorableUse(MO))) in PerformSinkAndFold()
435 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in PerformSinkAndFold()
437 UsedRegA == 0 ? nullptr : MRI->getRegClass(UsedRegA); in PerformSinkAndFold()
439 UsedRegB == 0 ? nullptr : MRI->getRegClass(UsedRegB); in PerformSinkAndFold()
445 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { in PerformSinkAndFold()
460 if (!TII->isAsCheapAsAMove(MI)) in PerformSinkAndFold()
464 if (!RC->contains(DstReg)) in PerformSinkAndFold()
468 if (!TII->canFoldIntoAddrMode(UseInst, Reg, MI, AM)) in PerformSinkAndFold()
479 const TargetRegisterClass *RCS = MRI->getRegClass(Reg); in PerformSinkAndFold()
480 if (RCA && RCA->hasSuperClassEq(RCS)) in PerformSinkAndFold()
482 else if (RCB && RCB->hasSuperClassEq(RCS)) in PerformSinkAndFold()
517 SinkDst->dump()); in PerformSinkAndFold()
518 if (SinkDst->isCopy()) { in PerformSinkAndFold()
519 // TODO: After performing the sink-and-fold, the original instruction is in PerformSinkAndFold()
530 MachineBasicBlock::iterator InsertPt = SinkDst->getIterator(); in PerformSinkAndFold()
531 Register DstReg = SinkDst->getOperand(0).getReg(); in PerformSinkAndFold()
532 TII->reMaterialize(*SinkDst->getParent(), InsertPt, DstReg, 0, MI, *TRI); in PerformSinkAndFold()
534 if (!New->getDebugLoc()) in PerformSinkAndFold()
535 New->setDebugLoc(SinkDst->getDebugLoc()); in PerformSinkAndFold()
541 MRI->clearKillFlags(UsedRegA); in PerformSinkAndFold()
543 MRI->clearKillFlags(UsedRegB); in PerformSinkAndFold()
546 New = TII->emitLdStWithAddr(*SinkDst, MaybeAM); in PerformSinkAndFold()
552 MRI->clearKillFlags(R); in PerformSinkAndFold()
554 MRI->clearKillFlags(R); in PerformSinkAndFold()
556 LLVM_DEBUG(dbgs() << "yielding"; New->dump()); in PerformSinkAndFold()
558 if (SinkDst->mayStore() && !SinkDst->hasOrderedMemoryRef()) in PerformSinkAndFold()
560 SinkDst->eraseFromParent(); in PerformSinkAndFold()
570 for (MachineOperand &MO : MRI->use_operands(Reg)) { in PerformSinkAndFold()
572 assert((U->isCopy() || U->isDebugInstr()) && in PerformSinkAndFold()
574 if (U->isCopy()) in PerformSinkAndFold()
575 Worklist.push_back(U->getOperand(0).getReg()); in PerformSinkAndFold()
582 MachineInstr *I = MO->getParent(); in PerformSinkAndFold()
583 if (I->isCopy()) { in PerformSinkAndFold()
584 I->eraseFromParent(); in PerformSinkAndFold()
586 MO->setReg(0); in PerformSinkAndFold()
587 MO->setSubReg(0); in PerformSinkAndFold()
595 /// AllUsesDominatedByBlock - Return true if all uses of the specified register
607 if (MRI->use_nodbg_empty(Reg)) in AllUsesDominatedByBlock()
611 // into and they are all PHI nodes. In this case, machine-sink must break in AllUsesDominatedByBlock()
617 // %def = DEC64_32r %x, implicit-def dead %eflags in AllUsesDominatedByBlock()
624 if (all_of(MRI->use_nodbg_operands(Reg), [&](MachineOperand &MO) { in AllUsesDominatedByBlock()
627 MachineBasicBlock *UseBlock = UseInst->getParent(); in AllUsesDominatedByBlock()
628 return UseBlock == MBB && UseInst->isPHI() && in AllUsesDominatedByBlock()
629 UseInst->getOperand(OpNo + 1).getMBB() == DefMBB; in AllUsesDominatedByBlock()
635 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { in AllUsesDominatedByBlock()
638 unsigned OpNo = &MO - &UseInst->getOperand(0); in AllUsesDominatedByBlock()
639 MachineBasicBlock *UseBlock = UseInst->getParent(); in AllUsesDominatedByBlock()
640 if (UseInst->isPHI()) { in AllUsesDominatedByBlock()
643 UseBlock = UseInst->getOperand(OpNo+1).getMBB(); in AllUsesDominatedByBlock()
650 if (!DT->dominates(MBB, UseBlock)) in AllUsesDominatedByBlock()
668 if (const PseudoSourceValue *PSV = MemOp->getPseudoValue()) in mayLoadFromGOTOrConstantPool()
669 if (PSV->isGOT() || PSV->isConstantPool()) in mayLoadFromGOTOrConstantPool()
680 if (!TII->shouldSink(MI)) { in FindCycleSinkCandidates()
704 if (!MRI->hasOneDef(MO.getReg())) in FindCycleSinkCandidates()
719 TII = STI->getInstrInfo(); in runOnMachineFunction()
720 TRI = STI->getRegisterInfo(); in runOnMachineFunction()
732 EnableSinkAndFold = PassConfig->getEnableSinkAndFold(); in runOnMachineFunction()
748 auto NewSucc = Pair.first->SplitCriticalEdge(Pair.second, *this); in runOnMachineFunction()
751 << printMBBReference(*Pair.first) << " -- " in runOnMachineFunction()
752 << printMBBReference(*NewSucc) << " -- " in runOnMachineFunction()
755 MBFI->onEdgeSplit(*Pair.first, *NewSucc, *MBPI); in runOnMachineFunction()
759 CI->splitCriticalEdge(Pair.first, Pair.second, NewSucc); in runOnMachineFunction()
769 SmallVector<MachineCycle *, 8> Cycles(CI->toplevel_begin(), in runOnMachineFunction()
770 CI->toplevel_end()); in runOnMachineFunction()
772 MachineBasicBlock *Preheader = Cycle->getCyclePreheader(); in runOnMachineFunction()
781 // of a def-use chain, if there is any. in runOnMachineFunction()
782 // TODO: Sort the candidates using a cost-model. in runOnMachineFunction()
804 MRI->clearKillFlags(I); in runOnMachineFunction()
817 if (!DT->isReachableFromEntry(&MBB)) return false; in ProcessBlock()
824 // Walk the basic block bottom-up. Remember if we saw a store. in ProcessBlock()
826 --I; in ProcessBlock()
835 --I; in ProcessBlock()
878 MI.getDebugLoc()->getInlinedAt()); in ProcessDbgInst()
886 // Record the variable for any DBG_VALUE, to avoid re-ordering any of them. in ProcessDbgInst()
901 if (!MI.isCopy() && !TII->isAsCheapAsAMove(MI)) in isWorthBreakingCriticalEdge()
913 Register SrcReg = Reg.isVirtual() ? TRI->lookThruCopyLike(Reg, MRI) : Reg; in isWorthBreakingCriticalEdge()
920 DeferredFromBlock = Res.first->second; in isWorthBreakingCriticalEdge()
925 if (From->isSuccessor(To) && MBPI->getEdgeProbability(From, To) <= in isWorthBreakingCriticalEdge()
945 if (MRI->hasOneNonDBGUse(Reg)) { in isWorthBreakingCriticalEdge()
950 MachineInstr *DefMI = MRI->getVRegDef(Reg); in isWorthBreakingCriticalEdge()
951 if (DefMI->getParent() == MI.getParent()) in isWorthBreakingCriticalEdge()
964 if (!SplitEdges || FromBB == ToBB || !FromBB->isSuccessor(ToBB)) in isLegalToBreakCriticalEdge()
967 MachineCycle *FromCycle = CI->getCycle(FromBB); in isLegalToBreakCriticalEdge()
968 MachineCycle *ToCycle = CI->getCycle(ToBB); in isLegalToBreakCriticalEdge()
972 (!FromCycle->isReducible() || FromCycle->getHeader() == ToBB)) in isLegalToBreakCriticalEdge()
989 // If %bb.1 -> %bb.3 edge is broken and computation of v1024 is inserted: in isLegalToBreakCriticalEdge()
1004 // This is incorrect since v1024 is not computed along the %bb.1->%bb.2->%bb.3 in isLegalToBreakCriticalEdge()
1015 for (MachineBasicBlock *Pred : ToBB->predecessors()) in isLegalToBreakCriticalEdge()
1016 if (Pred != FromBB && !DT->dominates(ToBB, Pred)) in isLegalToBreakCriticalEdge()
1054 return RP->second; in getBBRegisterPressure()
1065 MII != MIE; --MII) { in getBBRegisterPressure()
1079 return It.first->second; in getBBRegisterPressure()
1085 unsigned Weight = NRegs * TRI->getRegClassWeight(RC).RegWeight; in registerPressureSetExceedsLimit()
1086 const int *PS = TRI->getRegClassPressureSets(RC); in registerPressureSetExceedsLimit()
1088 for (; *PS != -1; PS++) in registerPressureSetExceedsLimit()
1090 TRI->getRegPressureSetLimit(*MBB.getParent(), *PS)) in registerPressureSetExceedsLimit()
1095 /// isProfitableToSinkTo - Return true if it is profitable to sink MI.
1106 if (!PDT->dominates(SuccToSinkTo, MBB)) in isProfitableToSinkTo()
1110 // cycle, even if the latter post-dominates the former (PR21115). in isProfitableToSinkTo()
1111 if (CI->getCycleDepth(MBB) > CI->getCycleDepth(SuccToSinkTo)) in isProfitableToSinkTo()
1116 for (MachineInstr &UseInst : MRI->use_nodbg_instructions(Reg)) { in isProfitableToSinkTo()
1127 // FIXME - If finding successor is compile time expensive then cache results. in isProfitableToSinkTo()
1132 MachineCycle *MCycle = CI->getCycle(MBB); in isProfitableToSinkTo()
1142 // Ignore non-register operands. in isProfitableToSinkTo()
1150 // Don't handle non-constant and non-ignorable physical register uses. in isProfitableToSinkTo()
1151 if (MO.isUse() && !MRI->isConstantPhysReg(Reg) && !TII->isIgnorableUse(MO)) in isProfitableToSinkTo()
1164 MachineInstr *DefMI = MRI->getVRegDef(Reg); in isProfitableToSinkTo()
1167 MachineCycle *Cycle = CI->getCycle(DefMI->getParent()); in isProfitableToSinkTo()
1172 if (Cycle != MCycle || (DefMI->isPHI() && Cycle && Cycle->isReducible() && in isProfitableToSinkTo()
1173 Cycle->getHeader() == DefMI->getParent())) in isProfitableToSinkTo()
1178 if (registerPressureSetExceedsLimit(1, MRI->getRegClass(Reg), in isProfitableToSinkTo()
1200 return Succs->second; in GetAllSortedSuccessors()
1202 SmallVector<MachineBasicBlock *, 4> AllSuccs(MBB->successors()); in GetAllSortedSuccessors()
1211 for (MachineDomTreeNode *DTChild : DT->getNode(MBB)->children()) { in GetAllSortedSuccessors()
1213 if (DTChild->getIDom()->getBlock() == MI.getParent() && in GetAllSortedSuccessors()
1215 !MBB->isSuccessor(DTChild->getBlock())) in GetAllSortedSuccessors()
1216 AllSuccs.push_back(DTChild->getBlock()); in GetAllSortedSuccessors()
1222 uint64_t LHSFreq = MBFI ? MBFI->getBlockFreq(L).getFrequency() : 0; in GetAllSortedSuccessors()
1223 uint64_t RHSFreq = MBFI ? MBFI->getBlockFreq(R).getFrequency() : 0; in GetAllSortedSuccessors()
1226 : CI->getCycleDepth(L) < CI->getCycleDepth(R); in GetAllSortedSuccessors()
1231 return it.first->second; in GetAllSortedSuccessors()
1234 /// FindSuccToSinkTo - Find a successor to sink this instruction to.
1244 // SuccToSinkTo - This is the successor to sink this instruction to, once we in FindSuccToSinkTo()
1248 if (!MO.isReg()) continue; // Ignore non-register operands. in FindSuccToSinkTo()
1258 if (!MRI->isConstantPhysReg(Reg) && !TII->isIgnorableUse(MO)) in FindSuccToSinkTo()
1269 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg))) in FindSuccToSinkTo()
1317 if (SuccToSinkTo && SuccToSinkTo->isEHPad()) in FindSuccToSinkTo()
1324 if (SuccToSinkTo && SuccToSinkTo->isInlineAsmBrIndirectTarget()) in FindSuccToSinkTo()
1327 if (SuccToSinkTo && !TII->isSafeToSink(MI, SuccToSinkTo, CI)) in FindSuccToSinkTo()
1346 if (MBB->pred_size() != 1) in SinkingPreventsImplicitNullCheck()
1349 auto *PredMBB = *MBB->pred_begin(); in SinkingPreventsImplicitNullCheck()
1350 auto *PredBB = PredMBB->getBasicBlock(); in SinkingPreventsImplicitNullCheck()
1356 !PredBB->getTerminator()->getMetadata(LLVMContext::MD_make_implicit)) in SinkingPreventsImplicitNullCheck()
1362 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in SinkingPreventsImplicitNullCheck()
1365 if (!BaseOp->isReg()) in SinkingPreventsImplicitNullCheck()
1372 if (TII->analyzeBranchPredicate(*PredMBB, MBP, false)) in SinkingPreventsImplicitNullCheck()
1378 MBP.LHS.getReg() == BaseOp->getReg(); in SinkingPreventsImplicitNullCheck()
1381 /// If the sunk instruction is a copy, try to forward the copy instead of
1387 const MachineRegisterInfo &MRI = SinkInst.getMF()->getRegInfo(); in attemptDebugCopyProp()
1388 const TargetInstrInfo &TII = *SinkInst.getMF()->getSubtarget().getInstrInfo(); in attemptDebugCopyProp()
1391 // see whether this is something that can be copy-forwarded. If it isn't, in attemptDebugCopyProp()
1398 SrcMO = CopyOperands->Source; in attemptDebugCopyProp()
1399 DstMO = CopyOperands->Destination; in attemptDebugCopyProp()
1404 // Trying to forward between physical and virtual registers is too hard. in attemptDebugCopyProp()
1405 if (Reg.isVirtual() != SrcMO->getReg().isVirtual()) in attemptDebugCopyProp()
1408 // Only try virtual register copy-forwarding before regalloc, and physical in attemptDebugCopyProp()
1409 // register copy-forwarding after regalloc. in attemptDebugCopyProp()
1414 // Pre-regalloc, only forward if all subregisters agree (or there are no in attemptDebugCopyProp()
1418 if (DbgMO.getSubReg() != SrcMO->getSubReg() || in attemptDebugCopyProp()
1419 DbgMO.getSubReg() != DstMO->getSubReg()) in attemptDebugCopyProp()
1422 // Post-regalloc, we may be sinking a DBG_VALUE of a sub or super-register in attemptDebugCopyProp()
1423 // of this copy. Only forward the copy if the DBG_VALUE operand exactly in attemptDebugCopyProp()
1425 if (PostRA && Reg != DstMO->getReg()) in attemptDebugCopyProp()
1429 DbgMO.setReg(SrcMO->getReg()); in attemptDebugCopyProp()
1430 DbgMO.setSubReg(SrcMO->getSubReg()); in attemptDebugCopyProp()
1441 // location to prevent debug-info driven tools from potentially reporting in performSink()
1445 InsertPos->getDebugLoc())); in performSink()
1460 MachineInstr *NewDbgMI = DbgMI->getMF()->CloneMachineInstr(DbgMI); in performSink()
1465 if (DbgMI->hasDebugOperandForReg(Reg)) { in performSink()
1473 DbgMI->setDebugValueUndef(); in performSink()
1477 /// hasStoreBetween - check if there is store betweeen straight line blocks From
1481 // Make sure From and To are in straight line which means From dominates To in hasStoreBetween()
1483 if (!DT->dominates(From, To) || !PDT->dominates(To, From)) in hasStoreBetween()
1491 return It->second; in hasStoreBetween()
1494 return llvm::any_of(It->second, [&](MachineInstr *I) { in hasStoreBetween()
1495 return I->mayAlias(AA, MI, false); in hasStoreBetween()
1517 if (PDT->dominates(To, BB)) { in hasStoreBetween()
1521 // If this BB is too big or the block number in straight line between From in hasStoreBetween()
1523 if (BB->sizeWithoutDebugLargerThan(SinkLoadInstsPerBlockThreshold) || in hasStoreBetween()
1526 if (DomBB != BB && DT->dominates(DomBB, BB)) in hasStoreBetween()
1528 else if(DomBB != BB && DT->dominates(BB, DomBB)) in hasStoreBetween()
1540 if (DomBB != BB && DT->dominates(DomBB, BB)) in hasStoreBetween()
1542 else if(DomBB != BB && DT->dominates(BB, DomBB)) in hasStoreBetween()
1573 MachineBasicBlock *Preheader = Cycle->getCyclePreheader(); in SinkIntoCycle()
1579 for (MachineInstr &MI : MRI->use_instructions(MO.getReg())) { in SinkIntoCycle()
1581 if (!Cycle->contains(MI.getParent())) { in SinkIntoCycle()
1602 SinkBlock = DT->findNearestCommonDominator(SinkBlock, MI.getParent()); in SinkIntoCycle()
1625 if (SinkBlock->sizeWithoutDebugLargerThan(SinkLoadInstsPerBlockThreshold)) { in SinkIntoCycle()
1632 SinkBlock->splice(SinkBlock->SkipPHIsAndLabels(SinkBlock->begin()), Preheader, in SinkIntoCycle()
1648 /// SinkInstruction - Determine whether it is safe to sink the specified machine
1653 if (!TII->shouldSink(MI)) in SinkInstruction()
1660 // Convergent operations may not be made control-dependent on additional in SinkInstruction()
1683 // If there are no outputs, it must have side-effects. in SinkInstruction()
1694 if (SuccToSinkTo->isLiveIn(Reg)) in SinkInstruction()
1702 if (SuccToSinkTo->pred_size() > 1) { in SinkInstruction()
1703 // We cannot sink a load across a critical edge - there may be stores in in SinkInstruction()
1715 if (!TryBreak && !DT->dominates(ParentBlock, SuccToSinkTo)) { in SinkInstruction()
1721 if (!TryBreak && CI->getCycle(SuccToSinkTo) && in SinkInstruction()
1722 (!CI->getCycle(SuccToSinkTo)->isReducible() || in SinkInstruction()
1723 CI->getCycle(SuccToSinkTo)->getHeader() == SuccToSinkTo)) { in SinkInstruction()
1747 // sunken into and they are all PHI nodes. In this case, machine-sink must in SinkInstruction()
1760 SuccToSinkTo->SkipPHIsAndLabels(SuccToSinkTo->begin()); in SinkInstruction()
1779 // This DBG_VALUE would re-order assignments. If we can't copy-propagate in SinkInstruction()
1782 DbgMI->setDebugValueUndef(); in SinkInstruction()
1791 // copy-propagate their operands. As it's expensive, don't do this if there's in SinkInstruction()
1793 if (MI.getMF()->getFunction().getSubprogram() && MI.isCopy()) in SinkInstruction()
1819 const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo(); in SalvageUnsunkDebugUsersOfCopy()
1825 if (!User.isDebugValue() || DT->dominates(TargetBlock, User.getParent())) in SalvageUnsunkDebugUsersOfCopy()
1828 // If is in same block, will either sink or be use-before-def. in SalvageUnsunkDebugUsersOfCopy()
1842 for (auto &DbgOp : User->getDebugOperandsForReg(Reg)) { in SalvageUnsunkDebugUsersOfCopy()
1850 //===----------------------------------------------------------------------===//
1852 // for the pre-ra machine sink pass. It is only designed to sink COPY
1856 // used in the current block and the COPY is live-in to a single successor
1868 // successor (%bb.1) because %w19 is only live-in in %bb.1.
1881 // As we sink %w19 (CSR in AArch64) into %bb.1, the shrink-wrapping pass will be
1883 //===----------------------------------------------------------------------===//
1924 INITIALIZE_PASS(PostRAMachineSinking, "postra-machine-sink",
1938 // Try to find a single sinkable successor in which Reg is live-in. in getSingleLiveInSuccBB()
1942 // If BB is set here, Reg is live-in to at least two sinkable successors, in getSingleLiveInSuccBB()
1949 // Reg is not live-in to any sinkable successors. in getSingleLiveInSuccBB()
1953 // Check if any register aliased with Reg is live-in in other successors. in getSingleLiveInSuccBB()
1982 MachineOperand &MO = MI->getOperand(U); in clearKillFlags()
1985 MachineBasicBlock::iterator NI = std::next(MI->getIterator()); in clearKillFlags()
2000 MachineFunction &MF = *SuccBB->getParent(); in updateLiveIn()
2003 for (MCPhysReg S : TRI->subregs_inclusive(DefReg)) in updateLiveIn()
2004 SuccBB->removeLiveIn(S); in updateLiveIn()
2006 SuccBB->addLiveIn(MI->getOperand(U).getReg()); in updateLiveIn()
2007 SuccBB->sortUniqueLiveIns(); in updateLiveIn()
2016 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in hasRegisterDependency()
2017 MachineOperand &MO = MI->getOperand(i); in hasRegisterDependency()
2054 if (!SI->livein_empty() && SI->pred_size() == 1) in tryToSinkCopy()
2090 for (MCRegUnit Unit : TRI->regunits(MO.getReg())) in tryToSinkCopy()
2127 // is live-in. in tryToSinkCopy()
2133 assert((SuccBB->pred_size() == 1 && *SuccBB->pred_begin() == &CurBB) && in tryToSinkCopy()
2141 for (MCRegUnit Unit : TRI->regunits(MO.getReg())) { in tryToSinkCopy()
2154 SuccBB->SkipPHIsAndLabels(SuccBB->begin()); in tryToSinkCopy()