331   LoopCarriedOrderDepsTracker(SwingSchedulerDAG *SSD, BatchAAResults *BAA,
1001                      const SwingSchedulerDAG *SSD, bool PerformCheapCheck) {  in hasLoopCarriedMemDep()  argument
1032   if (!SSD->mayOverlapInLaterIter(&SrcMI, &DstMI))  in hasLoopCarriedMemDep()
1068     SwingSchedulerDAG *SSD, BatchAAResults *BAA, const TargetInstrInfo *TII,  in LoopCarriedOrderDepsTracker()  argument
1070     : DAG(SSD), BAA(BAA), SUnits(DAG->SUnits), N(SUnits.size()),  in LoopCarriedOrderDepsTracker()
1337 static void computeScheduledInsts(const SwingSchedulerDAG *SSD,  in computeScheduledInsts()  argument
1358     CycleInstrs = Schedule.reorderInstructions(SSD, CycleInstrs);  in computeScheduledInsts()
1768   bool detect(const SwingSchedulerDAG *SSD, SMSchedule &Schedule,  in detect()  argument
1775     computeScheduledInsts(SSD, Schedule, OrderedInsts, Stages);  in detect()
3303 void SMSchedule::orderDependence(const SwingSchedulerDAG *SSD, SUnit *SU,  in orderDependence()  argument
3312   const SwingSchedulerDDG *DDG = SSD->getDDG();  in orderDependence()
3325           if (Register NewReg = SSD->getInstrBaseReg(SU))  in orderDependence()
3361                  isLoopCarriedDefOfUse(SSD, (*I)->getInstr(), MO)) {  in orderDependence()
3420     orderDependence(SSD, UseSU, Insts);  in orderDependence()
3421     orderDependence(SSD, SU, Insts);  in orderDependence()
3422     orderDependence(SSD, DefSU, Insts);  in orderDependence()
3434 bool SMSchedule::isLoopCarried(const SwingSchedulerDAG *SSD,  in isLoopCarried()  argument
3439   SUnit *DefSU = SSD->getSUnit(&Phi);  in isLoopCarried()
3446   SUnit *UseSU = SSD->getSUnit(MRI.getVRegDef(LoopVal));  in isLoopCarried()
3463 bool SMSchedule::isLoopCarriedDefOfUse(const SwingSchedulerDAG *SSD,  in isLoopCarriedDefOfUse()  argument
3473   if (!isLoopCarried(SSD, *Phi))  in isLoopCarriedDefOfUse()
3495     SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI) {  in computeUnpipelineableNodes()  argument
3499   for (auto &SU : SSD->SUnits)  in computeUnpipelineableNodes()
3503   const SwingSchedulerDDG *DDG = SSD->getDDG();  in computeUnpipelineableNodes()
3525     SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI) {  in normalizeNonPipelinedInstructions()  argument
3526   SmallSet<SUnit *, 8> DNP = computeUnpipelineableNodes(SSD, PLI);  in normalizeNonPipelinedInstructions()
3529   for (SUnit &SU : SSD->SUnits) {  in normalizeNonPipelinedInstructions()
3539     for (const auto &IE : SSD->getDDG()->getInEdges(&SU))  in normalizeNonPipelinedInstructions()
3545     for (auto &OE : SSD->getDDG()->getOutEdges(&SU))  in normalizeNonPipelinedInstructions()
3599 bool SMSchedule::isValidSchedule(SwingSchedulerDAG *SSD) {  in isValidSchedule()  argument
3600   for (SUnit &SU : SSD->SUnits) {  in isValidSchedule()
3606     for (auto &OE : SSD->getDDG()->getOutEdges(&SU)) {  in isValidSchedule()
3769 SMSchedule::reorderInstructions(const SwingSchedulerDAG *SSD,  in reorderInstructions()  argument
3779       orderDependence(SSD, SU, NewOrderI);  in reorderInstructions()
3788 void SMSchedule::finalizeSchedule(SwingSchedulerDAG *SSD) {  in finalizeSchedule()  argument
3807   for (const SUnit &SU : SSD->SUnits)  in finalizeSchedule()
3808     SSD->applyInstrChange(SU.getInstr(), *this);  in finalizeSchedule()
3814     cycleInstrs = reorderInstructions(SSD, cycleInstrs);  in finalizeSchedule()
3815     SSD->fixupRegisterOverlaps(cycleInstrs);  in finalizeSchedule()