Lines Matching +full:keep +full:- +full:a +full:- +full:live
1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 // This class computes live variables using a sparse implementation based on
17 // the machine code SSA form. This class computes live variable information for
18 // each virtual and _register allocatable_ physical register in a function. It
19 // uses the dominance properties of SSA form to efficiently compute live
21 // live within a single basic block (allowing it to do a single local analysis
22 // to resolve physical register lifetimes in each basic block). If a physical
26 //===----------------------------------------------------------------------===//
37 #include "llvm/Config/llvm-config.h"
55 OS << "Live variables in machine function: " << MF.getName() << '\n'; in run()
63 "Live Variable Analysis", false, false)
66 "Live Variable Analysis", false, false) in INITIALIZE_PASS_DEPENDENCY()
90 if (MI->getParent() == MBB) in findKill()
113 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
115 assert(Reg.isVirtual() && "getVarInfo: not a virtual register!"); in getVarInfo()
123 unsigned BBNum = MBB->getNumber(); in MarkVirtRegAliveInBlock()
128 if (VRInfo.Kills[i]->getParent() == MBB) { in MarkVirtRegAliveInBlock()
136 return; // We already know the block is live in MarkVirtRegAliveInBlock()
141 assert(MBB != &MF->front() && "Can't find reaching def for virtreg"); in MarkVirtRegAliveInBlock()
142 WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend()); in MarkVirtRegAliveInBlock()
159 assert(MRI->getVRegDef(Reg) && "Register use before def!"); in HandleVirtRegUse()
161 unsigned BBNum = MBB->getNumber(); in HandleVirtRegUse()
165 // Check to see if this basic block is already a kill block. in HandleVirtRegUse()
166 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) { in HandleVirtRegUse()
168 // live range by updating the kill instruction. in HandleVirtRegUse()
175 assert(Kill->getParent() != MBB && "entry should be at end!"); in HandleVirtRegUse()
180 // ,------. in HandleVirtRegUse()
189 // `------' in HandleVirtRegUse()
191 // where there is a use in a PHI node that's a predecessor to the defining in HandleVirtRegUse()
194 if (MBB == MRI->getVRegDef(Reg)->getParent()) in HandleVirtRegUse()
197 // Add a new kill entry for this basic block. If this virtual register is in HandleVirtRegUse()
199 // least one of the successor blocks, it's not a kill. in HandleVirtRegUse()
203 // Update all dominating blocks to mark them as "known live". in HandleVirtRegUse()
204 for (MachineBasicBlock *Pred : MBB->predecessors()) in HandleVirtRegUse()
205 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), Pred); in HandleVirtRegUse()
216 /// FindLastPartialDef - Return the last partial def of the specified register.
217 /// Also returns the sub-registers that're defined by the instruction.
224 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in FindLastPartialDef()
240 for (MachineOperand &MO : LastDef->all_defs()) { in FindLastPartialDef()
244 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
245 for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg)) in FindLastPartialDef()
252 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
253 /// implicit defs to a machine instruction if there was an earlier def of its
254 /// super-register.
257 // If there was a previous use or a "full" def all is well. in HandlePhysRegUse()
259 // Otherwise, the last sub-register def implicitly defines this register. in HandlePhysRegUse()
262 // AL = ... implicit-def EAX, implicit killed AH in HandlePhysRegUse()
266 // All of the sub-registers must have been defined before the use of Reg! in HandlePhysRegUse()
269 // If LastPartialDef is NULL, it must be using a livein register. in HandlePhysRegUse()
271 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
275 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegUse()
282 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
286 for (MCPhysReg SS : TRI->subregs(SubReg)) in HandlePhysRegUse()
291 !LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr)) in HandlePhysRegUse()
293 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
297 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in HandlePhysRegUse()
301 /// FindLastRefOrPartRef - Return the last reference or partial reference of
312 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in FindLastRefOrPartRef()
315 // There was a def of this sub-register in between. This is a partial in FindLastRefOrPartRef()
316 // def, keep track of the last one. in FindLastRefOrPartRef()
354 // dead AX = implicit-def AL in HandlePhysRegKill()
360 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegKill()
363 // There was a def of this sub-register in between. This is a partial in HandlePhysRegKill()
364 // def, keep track of the last one. in HandlePhysRegKill()
373 for (MCPhysReg SS : TRI->subregs_inclusive(SubReg)) in HandlePhysRegKill()
385 // sub-registers which are used. in HandlePhysRegKill()
386 // dead EAX = op implicit-def AL in HandlePhysRegKill()
388 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true); in HandlePhysRegKill()
389 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegKill()
395 PhysRegDef[Reg]->findRegisterDefOperand(SubReg, /*TRI=*/nullptr); in HandlePhysRegKill()
398 assert(!MO->isDead()); in HandlePhysRegKill()
402 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
406 LastSubRef->addRegisterKilled(SubReg, TRI, true); in HandlePhysRegKill()
408 LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true); in HandlePhysRegKill()
409 for (MCPhysReg SS : TRI->subregs_inclusive(SubReg)) in HandlePhysRegKill()
412 for (MCPhysReg SS : TRI->subregs(SubReg)) in HandlePhysRegKill()
418 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
422 LastRefOrPartRef->findRegisterDefOperand(Reg, TRI, false, false); in HandlePhysRegKill()
423 bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg; in HandlePhysRegKill()
426 LastRefOrPartRef->addRegisterDead(Reg, TRI, true); in HandlePhysRegKill()
428 // If we are adding a subreg def and the superreg def is marked early in HandlePhysRegKill()
430 MO = LastRefOrPartRef->findRegisterDefOperand(Reg, /*TRI=*/nullptr); in HandlePhysRegKill()
432 MO->setIsEarlyClobber(); in HandlePhysRegKill()
436 LastRefOrPartRef->addRegisterKilled(Reg, TRI, true); in HandlePhysRegKill()
441 // Call HandlePhysRegKill() for all live registers clobbered by Mask. in HandleRegMask()
448 // Skip mask-preserved regs. in HandleRegMask()
451 // Kill the largest clobbered super-register. in HandleRegMask()
454 for (MCPhysReg SR : TRI->superregs(Reg)) in HandleRegMask()
465 SmallSet<unsigned, 32> Live; in HandlePhysRegDef() local
467 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in HandlePhysRegDef()
468 Live.insert(SubReg); in HandlePhysRegDef()
470 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegDef()
471 // If a register isn't itself defined, but all parts that make up of it in HandlePhysRegDef()
477 if (Live.count(SubReg)) in HandlePhysRegDef()
480 for (MCPhysReg SS : TRI->subregs_inclusive(SubReg)) in HandlePhysRegDef()
481 Live.insert(SS); in HandlePhysRegDef()
489 // Only some of the sub-registers are used. in HandlePhysRegDef()
490 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegDef()
491 if (!Live.count(SubReg)) in HandlePhysRegDef()
492 // Skip if this sub-register isn't defined. in HandlePhysRegDef()
505 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) { in UpdatePhysRegDefs()
519 // Unless it is a PHI node. In this case, ONLY process the DEF, not any in runOnInstr()
538 if (!(MOReg.isPhysical() && MRI->isReserved(MOReg))) in runOnInstr()
546 if (MOReg.isPhysical() && !MRI->isReserved(MOReg)) in runOnInstr()
557 else if (!MRI->isReserved(MOReg)) in runOnInstr()
569 else if (!MRI->isReserved(MOReg)) in runOnInstr()
576 // Mark live-in registers as live-in. in runOnBlock()
578 for (const auto &LI : MBB->liveins()) { in runOnBlock()
580 "Cannot have a live-in virtual register!"); in runOnBlock()
599 if (!PHIVarInfo[MBB->getNumber()].empty()) { in runOnBlock()
600 SmallVectorImpl<unsigned> &VarInfoVec = PHIVarInfo[MBB->getNumber()]; in runOnBlock()
604 MarkVirtRegAliveInBlock(getVarInfo(I), MRI->getVRegDef(I)->getParent(), in runOnBlock()
608 // MachineCSE may CSE instructions which write to non-allocatable physical in runOnBlock()
611 for (const MachineBasicBlock *SuccMBB : MBB->successors()) { in runOnBlock()
612 if (SuccMBB->isEHPad()) in runOnBlock()
614 for (const auto &LI : SuccMBB->liveins()) { in runOnBlock()
615 if (!TRI->isInAllocatableClass(LI.PhysReg)) in runOnBlock()
616 // Ignore other live-ins, e.g. those that are live into landing pads. in runOnBlock()
631 TRI = MF->getSubtarget().getRegisterInfo(); in analyze()
633 const unsigned NumRegs = TRI->getNumSupportedRegs(mf); in analyze()
636 PHIVarInfo.resize(MF->getNumBlockIDs()); in analyze()
640 // dependencies. Until then, we can't change much in -O0. in analyze()
641 if (!MRI->isSSA()) in analyze()
642 report_fatal_error("regalloc=... not currently supported with -O0"); in analyze()
646 // Calculate live variable information in depth first order on the CFG of the in analyze()
647 // function. This guarantees that we will see the definition of a virtual in analyze()
649 // nodes, which are treated as a special case). in analyze()
650 MachineBasicBlock *Entry = &MF->front(); in analyze()
665 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg)) in analyze()
666 VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI); in analyze()
668 VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI); in analyze()
672 // function. If so, it is due to a bug in the instruction selector or some in analyze()
691 MachineInstr &DefMI = *MRI->getUniqueVRegDef(Reg); in recomputeForSingleDefVirtReg()
694 // Initialize a worklist of BBs that Reg is live-to-end of. (Here in recomputeForSingleDefVirtReg()
695 // "live-to-end" means Reg is live at the end of a block even if it is only in recomputeForSingleDefVirtReg()
696 // live because of phi uses in a successor. This is different from isLiveOut() in recomputeForSingleDefVirtReg()
701 for (auto &UseMO : MRI->use_nodbg_operands(Reg)) { in recomputeForSingleDefVirtReg()
710 // If Reg is used in a phi then it is live-to-end of the corresponding in recomputeForSingleDefVirtReg()
715 // A non-phi use in the same BB as the single def must come after the def. in recomputeForSingleDefVirtReg()
717 // Otherwise Reg must be live-to-end of all predecessors. in recomputeForSingleDefVirtReg()
745 // live-through, find the last instruction that uses Reg. Ignore phi nodes in recomputeForSingleDefVirtReg()
750 MachineBasicBlock &UseBB = *MF->getBlockNumbered(UseBBNum); in recomputeForSingleDefVirtReg()
768 /// replaceKillInstruction - Update register kill info by replacing a kill
769 /// instruction with a new one.
776 /// removeVirtualRegistersKilled - Remove all killed info for the specified
792 /// analyzePHINodes - Gather information about the PHI nodes in here. In
793 /// particular, we want to map the variable information of a virtual register
794 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
803 PHIVarInfo[BBI.getOperand(i + 1).getMBB()->getNumber()] in analyzePHINodes()
812 // Reg is live-through. in isLiveIn()
816 // Registers defined in MBB cannot be live in. in isLiveIn()
818 if (Def && Def->getParent() == &MBB) in isLiveIn()
830 Kills.insert(MI->getParent()); in isLiveOut()
833 // the value is either live in the block, or if it is killed in the block. in isLiveOut()
836 unsigned SuccIdx = SuccMBB->getNumber(); in isLiveOut()
839 // Or is it live because there is a use in a successor that kills it? in isLiveOut()
847 /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
848 /// variables that are live out of DomBB will be marked as passing live through
853 const unsigned NumNew = BB->getNumber(); in addNewBlock()
857 MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end(); in addNewBlock()
858 for (; BBI != BBE && BBI->isPHI(); ++BBI) { in addNewBlock()
860 Defs.insert(BBI->getOperand(0).getReg()); in addNewBlock()
862 // All registers used by PHI nodes in SuccBB must be live through BB. in addNewBlock()
863 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) in addNewBlock()
864 if (BBI->getOperand(i+1).getMBB() == BB) in addNewBlock()
865 getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew); in addNewBlock()
870 for (const MachineOperand &Op : BBI->operands()) { in addNewBlock()
880 // Update info for all live variables in addNewBlock()
881 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in addNewBlock()
884 // If the Defs is defined in the successor it can't be live in BB. in addNewBlock()
888 // If the register is either killed in or live through SuccBB it's also live in addNewBlock()
891 if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber())) in addNewBlock()
896 /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
897 /// variables that are live out of DomBB will be marked as passing live through
904 const unsigned NumNew = BB->getNumber(); in addNewBlock()
906 SparseBitVector<> &BV = LiveInSets[SuccBB->getNumber()]; in addNewBlock()
912 // All registers used by PHI nodes in SuccBB must be live through BB. in addNewBlock()
913 for (MachineBasicBlock::iterator BBI = SuccBB->begin(), in addNewBlock()
914 BBE = SuccBB->end(); in addNewBlock()
915 BBI != BBE && BBI->isPHI(); ++BBI) { in addNewBlock()
916 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) in addNewBlock()
917 if (BBI->getOperand(i + 1).getMBB() == BB && in addNewBlock()
918 BBI->getOperand(i).readsReg()) in addNewBlock()
919 getVarInfo(BBI->getOperand(i).getReg()) in addNewBlock()