1 //===- InitUndef.cpp - Initialize undef value to pseudo ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 // Certain instructions have register overlapping constraints, and
28 // when program encounter operation that has early-clobber constraint.
31 // See also: https://github.com/llvm/llvm-project/issues/50157
34 // from NoReg to IMPLICIT_DEF.  (Not that this is a non-overlapping set of
39 //===----------------------------------------------------------------------===//
57 #define DEBUG_TYPE "init-undef"
107   for (auto &DefMI : MRI->def_instructions(Reg)) {  in findImplictDefMIFromReg()
116   for (auto &UseMO : MI->uses()) {  in handleReg()
123     if (!TRI->doesRegClassHavePseudoInitUndef(MRI->getRegClass(UseMO.getReg())))  in handleReg()
143     if (!TRI->doesRegClassHavePseudoInitUndef(MRI->getRegClass(UseMO.getReg())))  in handleSubReg()
156         TRI->getLargestSuperClass(MRI->getRegClass(Reg));  in handleSubReg()
169     TRI->getCoveringSubRegIndexes(*MRI, TargetRegClass, NeedDef,  in handleSubReg()
175       const TargetRegisterClass *SubRegClass = TRI->getLargestSuperClass(  in handleSubReg()
176           TRI->getSubRegisterClass(TargetRegClass, ind));  in handleSubReg()
177       Register TmpInitSubReg = MRI->createVirtualRegister(SubRegClass);  in handleSubReg()
178       LLVM_DEBUG(dbgs() << "Register Class ID" << SubRegClass->getID() << "\n");  in handleSubReg()
180               TII->get(TII->getUndefInitOpcode(SubRegClass->getID())),  in handleSubReg()
182       Register NewReg = MRI->createVirtualRegister(TargetRegClass);  in handleSubReg()
184               TII->get(TargetOpcode::INSERT_SUBREG), NewReg)  in handleSubReg()
204       TRI->getLargestSuperClass(MRI->getRegClass(MO.getReg()));  in fixupIllOperand()
205   LLVM_DEBUG(dbgs() << "Register Class ID" << TargetRegClass->getID() << "\n");  in fixupIllOperand()
206   unsigned Opcode = TII->getUndefInitOpcode(TargetRegClass->getID());  in fixupIllOperand()
207   Register NewReg = MRI->createVirtualRegister(TargetRegClass);  in fixupIllOperand()
208   BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(Opcode), NewReg);  in fixupIllOperand()
228             TII->getRegClass(MI.getDesc(), UseOpIdx, TRI, MF);  in processBasicBlock()
229         Register NewDest = MRI->createVirtualRegister(RC);  in processBasicBlock()
233         BuildMI(MBB, I, I->getDebugLoc(), TII->get(TargetOpcode::IMPLICIT_DEF),  in processBasicBlock()
241       if (MRI->subRegLivenessEnabled())  in processBasicBlock()
258   if (!ST->supportsInitUndef())  in runOnMachineFunction()
262   TII = ST->getInstrInfo();  in runOnMachineFunction()
263   TRI = MRI->getTargetRegisterInfo();  in runOnMachineFunction()
273     DeadMI->eraseFromParent();  in runOnMachineFunction()