Lines Matching refs:RevCond
1052 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); in AnalyzeBranches() local
1053 BBI.IsBrReversible = (RevCond.size() == 0) || in AnalyzeBranches()
1054 !TII->reverseBranchCondition(RevCond); in AnalyzeBranches()
1300 RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); in AnalyzeBlock() local
1301 bool CanRevCond = !TII->reverseBranchCondition(RevCond); in AnalyzeBlock()
1319 bool FalseFeasible = FeasibilityAnalysis(FalseBBI, RevCond, in AnalyzeBlock()
1410 FeasibilityAnalysis(FalseBBI, RevCond, true)) { in AnalyzeBlock()
1421 FeasibilityAnalysis(FalseBBI, RevCond, true, true)) { in AnalyzeBlock()
1431 FeasibilityAnalysis(FalseBBI, RevCond)) { in AnalyzeBlock()
1709 SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(), in IfConvertTriangle() local
1711 if (TII->reverseBranchCondition(RevCond)) in IfConvertTriangle()
1727 TII->insertBranch(*BBI.BB, CvtBBI->FalseBB, nullptr, RevCond, dl); in IfConvertTriangle()
1800 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); in IfConvertDiamondCommon() local
1801 if (TII->reverseBranchCondition(RevCond)) in IfConvertDiamondCommon()
1804 SmallVector<MachineOperand, 4> *Cond2 = &RevCond; in IfConvertDiamondCommon()