60     const TargetRegisterClass &RegClass, MachineOperand &RegMO) {  in constrainOperandRegClass()  argument
61   Register Reg = RegMO.getReg();  in constrainOperandRegClass()
78     if (RegMO.isUse()) {  in constrainOperandRegClass()
83       assert(RegMO.isDef() && "Must be a definition");  in constrainOperandRegClass()
89       Observer->changingInstr(*RegMO.getParent());  in constrainOperandRegClass()
91     RegMO.setReg(ConstrainedReg);  in constrainOperandRegClass()
93       Observer->changedInstr(*RegMO.getParent());  in constrainOperandRegClass()
97       if (!RegMO.isDef()) {  in constrainOperandRegClass()
112     MachineOperand &RegMO, unsigned OpIdx) {  in constrainOperandRegClass()  argument
113   Register Reg = RegMO.getReg();  in constrainOperandRegClass()
129             OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI)))  in constrainOperandRegClass()
136     assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&  in constrainOperandRegClass()
152                                   RegMO);  in constrainOperandRegClass()