Lines Matching refs:CarryIn
2185 std::optional<Register> CarryIn; in widenScalarAddSubOverflow() local
2208 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
2213 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
2218 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
2223 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
2231 if (CarryIn) in widenScalarAddSubOverflow()
2243 if (CarryIn) { in widenScalarAddSubOverflow()
2247 {LHSExt, RHSExt, *CarryIn}) in widenScalarAddSubOverflow()
3928 auto [Res, CarryOut, LHS, RHS, CarryIn] = MI.getFirst5Regs(); in lower()
3941 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); in lower()
3949 auto Carry2 = MIRBuilder.buildAnd(CondTy, ResEqZero, CarryIn); in lower()
5917 Register CarryDst, CarryIn; in narrowScalarAddSub() local
5921 CarryIn = MI.getOperand(NumDefs + 2).getReg(); in narrowScalarAddSub()
5946 if (!CarryIn) { in narrowScalarAddSub()
5951 {Src1Regs[i], Src2Regs[i], CarryIn}); in narrowScalarAddSub()
5954 {Src1Regs[i], Src2Regs[i], CarryIn}); in narrowScalarAddSub()
5958 CarryIn = CarryOut; in narrowScalarAddSub()