Lines Matching refs:getOrCreateVReg
306 Register Op0 = getOrCreateVReg(*U.getOperand(0)); in translateBinaryOp()
307 Register Op1 = getOrCreateVReg(*U.getOperand(1)); in translateBinaryOp()
308 Register Res = getOrCreateVReg(U); in translateBinaryOp()
321 Register Op0 = getOrCreateVReg(*U.getOperand(0)); in translateUnaryOp()
322 Register Res = getOrCreateVReg(U); in translateUnaryOp()
339 Register Op0 = getOrCreateVReg(*U.getOperand(0)); in translateCompare()
340 Register Op1 = getOrCreateVReg(*U.getOperand(1)); in translateCompare()
341 Register Res = getOrCreateVReg(U); in translateCompare()
347 Res, getOrCreateVReg(*Constant::getNullValue(U.getType()))); in translateCompare()
350 Res, getOrCreateVReg(*Constant::getAllOnesValue(U.getType()))); in translateCompare()
863 Register SwitchOpReg = getOrCreateVReg(SValue); in emitJumpTableHeader()
884 auto Cst = getOrCreateVReg( in emitJumpTableHeader()
900 Register CondLHS = getOrCreateVReg(*CB.CmpLHS); in emitSwitchCase()
929 Register CondRHS = getOrCreateVReg(*CB.CmpRHS); in emitSwitchCase()
944 Register CmpOpReg = getOrCreateVReg(*CB.CmpMHS); in emitSwitchCase()
946 Register CondRHS = getOrCreateVReg(*CB.CmpRHS); in emitSwitchCase()
1088 Register SwitchOpReg = getOrCreateVReg(*B.SValue); in emitBitTestHeader()
1336 const Register Tgt = getOrCreateVReg(*BrInst.getAddress()); in translateIndirectBr()
1370 Register Base = getOrCreateVReg(*LI.getPointerOperand()); in translateLoad()
1419 Register Base = getOrCreateVReg(*SI.getPointerOperand()); in translateStore()
1511 Register Tst = getOrCreateVReg(*U.getOperand(0)); in translateSelect()
1529 Register Src = getOrCreateVReg(V); in translateCopy()
1568 Register Op = getOrCreateVReg(*U.getOperand(0)); in translateCast()
1569 Register Res = getOrCreateVReg(U); in translateCast()
1577 Register BaseReg = getOrCreateVReg(Op0); in translateGetElementPtr()
1640 Register IdxReg = getOrCreateVReg(*Idx); in translateGetElementPtr()
1675 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0), in translateGetElementPtr()
1680 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
1696 Register SrcReg = getOrCreateVReg(**AI); in translateMemFunc()
1806 Register Op0 = getOrCreateVReg(*CI.getOperand(0)); in translateVectorInterleave2Intrinsic()
1807 Register Op1 = getOrCreateVReg(*CI.getOperand(1)); in translateVectorInterleave2Intrinsic()
1808 Register Res = getOrCreateVReg(CI); in translateVectorInterleave2Intrinsic()
1823 Register Op = getOrCreateVReg(*CI.getOperand(0)); in translateVectorDeinterleave2Intrinsic()
1863 {getOrCreateVReg(*CI.getOperand(0)), getOrCreateVReg(*CI.getOperand(1))}); in translateOverflowIntrinsic()
1870 Register Dst = getOrCreateVReg(CI); in translateFixedPointIntrinsic()
1871 Register Src0 = getOrCreateVReg(*CI.getOperand(0)); in translateFixedPointIntrinsic()
1872 Register Src1 = getOrCreateVReg(*CI.getOperand(1)); in translateFixedPointIntrinsic()
2024 VRegs.push_back(getOrCreateVReg(*Arg)); in translateSimpleIntrinsic()
2026 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs, in translateSimpleIntrinsic()
2069 VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(I))); in translateConstrainedFPIntrinsic()
2071 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags); in translateConstrainedFPIntrinsic()
2223 MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)}) in translateKnownIntrinsic()
2296 Register Dst = getOrCreateVReg(CI); in translateKnownIntrinsic()
2297 Register Op0 = getOrCreateVReg(*CI.getArgOperand(0)); in translateKnownIntrinsic()
2298 Register Op1 = getOrCreateVReg(*CI.getArgOperand(1)); in translateKnownIntrinsic()
2299 Register Op2 = getOrCreateVReg(*CI.getArgOperand(2)); in translateKnownIntrinsic()
2318 MIRBuilder.buildFPExt(getOrCreateVReg(CI), in translateKnownIntrinsic()
2319 getOrCreateVReg(*CI.getArgOperand(0)), in translateKnownIntrinsic()
2324 MIRBuilder.buildFPTrunc(getOrCreateVReg(CI), in translateKnownIntrinsic()
2325 getOrCreateVReg(*CI.getArgOperand(0)), in translateKnownIntrinsic()
2331 getOrCreateVReg(*CI.getArgOperand(0)), in translateKnownIntrinsic()
2345 Register Reg = getOrCreateVReg(CI); in translateKnownIntrinsic()
2357 getStackGuard(getOrCreateVReg(CI), MIRBuilder); in translateKnownIntrinsic()
2366 GuardVal = getOrCreateVReg(*CI.getArgOperand(0)); // The guard's value. in translateKnownIntrinsic()
2373 GuardVal, getOrCreateVReg(*Slot), in translateKnownIntrinsic()
2381 MIRBuilder.buildInstr(TargetOpcode::G_STACKSAVE, {getOrCreateVReg(CI)}, {}); in translateKnownIntrinsic()
2386 {getOrCreateVReg(*CI.getArgOperand(0))}); in translateKnownIntrinsic()
2398 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2399 {getOrCreateVReg(*CI.getArgOperand(0))}); in translateKnownIntrinsic()
2416 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2417 getOrCreateVReg(*CI.getArgOperand(0))); in translateKnownIntrinsic()
2430 .buildInstr(TargetOpcode::G_READ_REGISTER, {getOrCreateVReg(CI)}, {}) in translateKnownIntrinsic()
2438 .addUse(getOrCreateVReg(*CI.getArgOperand(1))); in translateKnownIntrinsic()
2471 Register Dst = getOrCreateVReg(CI); in translateKnownIntrinsic()
2472 Register ScalarSrc = getOrCreateVReg(*CI.getArgOperand(0)); in translateKnownIntrinsic()
2473 Register VecSrc = getOrCreateVReg(*CI.getArgOperand(1)); in translateKnownIntrinsic()
2510 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2511 getOrCreateVReg(*ConstantInt::getTrue(CI.getType()))); in translateKnownIntrinsic()
2526 {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2527 {getOrCreateVReg(*CI.getArgOperand(0))}, Flags) in translateKnownIntrinsic()
2537 .buildInstr(TargetOpcode::G_IS_FPCLASS, {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2538 {getOrCreateVReg(*FpValue)}) in translateKnownIntrinsic()
2545 MIRBuilder.buildSetFPEnv(getOrCreateVReg(*FPEnv)); in translateKnownIntrinsic()
2553 MIRBuilder.buildSetFPMode(getOrCreateVReg(*FPState)); in translateKnownIntrinsic()
2560 MIRBuilder.buildVScale(getOrCreateVReg(CI), 1); in translateKnownIntrinsic()
2564 MIRBuilder.buildSCmp(getOrCreateVReg(CI), in translateKnownIntrinsic()
2565 getOrCreateVReg(*CI.getOperand(0)), in translateKnownIntrinsic()
2566 getOrCreateVReg(*CI.getOperand(1))); in translateKnownIntrinsic()
2569 MIRBuilder.buildUCmp(getOrCreateVReg(CI), in translateKnownIntrinsic()
2570 getOrCreateVReg(*CI.getOperand(0)), in translateKnownIntrinsic()
2571 getOrCreateVReg(*CI.getOperand(1))); in translateKnownIntrinsic()
2583 MIRBuilder.buildPrefetch(getOrCreateVReg(*Addr), RW, Locality, CacheType, in translateKnownIntrinsic()
2677 Register DiscReg = getOrCreateVReg(*Discriminator); in translateCallBase()
2694 [&]() { return getOrCreateVReg(*CB.getCalledOperand()); }); in translateCallBase()
2811 Register TokenReg = getOrCreateVReg(*Token); in translateCall()
3039 Register Res = getOrCreateVReg(AI); in translateAlloca()
3050 Register NumElts = getOrCreateVReg(*AI.getArraySize()); in translateAlloca()
3063 getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, DL->getTypeAllocSize(Ty))); in translateAlloca()
3080 MIRBuilder.buildDynStackAlloc(getOrCreateVReg(AI), AlignedAlloc, Alignment); in translateAlloca()
3092 MIRBuilder.buildInstr(TargetOpcode::G_VAARG, {getOrCreateVReg(U)}, in translateVAArg()
3093 {getOrCreateVReg(*U.getOperand(0)), in translateVAArg()
3126 Register Res = getOrCreateVReg(U); in translateInsertElement()
3127 Register Val = getOrCreateVReg(*U.getOperand(0)); in translateInsertElement()
3128 Register Elt = getOrCreateVReg(*U.getOperand(1)); in translateInsertElement()
3135 Idx = getOrCreateVReg(*NewIdxCI); in translateInsertElement()
3139 Idx = getOrCreateVReg(*U.getOperand(2)); in translateInsertElement()
3155 Register Res = getOrCreateVReg(U); in translateExtractElement()
3156 Register Val = getOrCreateVReg(*U.getOperand(0)); in translateExtractElement()
3163 Idx = getOrCreateVReg(*NewIdxCI); in translateExtractElement()
3167 Idx = getOrCreateVReg(*U.getOperand(1)); in translateExtractElement()
3186 getOrCreateVReg(*Op0), 0); in translateShuffleVector()
3187 MIRBuilder.buildSplatVector(getOrCreateVReg(U), SplatVal); in translateShuffleVector()
3198 .buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {getOrCreateVReg(U)}, in translateShuffleVector()
3199 {getOrCreateVReg(*U.getOperand(0)), in translateShuffleVector()
3200 getOrCreateVReg(*U.getOperand(1))}) in translateShuffleVector()
3227 Register Addr = getOrCreateVReg(*I.getPointerOperand()); in translateAtomicCmpXchg()
3228 Register Cmp = getOrCreateVReg(*I.getCompareOperand()); in translateAtomicCmpXchg()
3229 Register NewVal = getOrCreateVReg(*I.getNewValOperand()); in translateAtomicCmpXchg()
3245 Register Res = getOrCreateVReg(I); in translateAtomicRMW()
3246 Register Addr = getOrCreateVReg(*I.getPointerOperand()); in translateAtomicRMW()
3247 Register Val = getOrCreateVReg(*I.getValOperand()); in translateAtomicRMW()
3449 MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address), in translateDbgDeclareRecord()
3514 Register Addr = getOrCreateVReg(*CPA->getPointer()); in translate()
3515 Register AddrDisc = getOrCreateVReg(*CPA->getAddrDiscriminator()); in translate()
3527 Ops.push_back(getOrCreateVReg(Elt)); in translate()
3537 Ops.push_back(getOrCreateVReg(Elt)); in translate()
3554 Ops.push_back(getOrCreateVReg(*CV->getOperand(i))); in translate()
3753 Register GuardPtr = getOrCreateVReg(*IRGuard); in emitSPDescriptorParent()