Lines Matching refs:Cases

546     const std::vector<SwitchCG::CaseBlock> &Cases) {  in shouldEmitAsBranches()  argument
548 if (Cases.size() != 2) in shouldEmitAsBranches()
553 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && in shouldEmitAsBranches()
554 Cases[0].CmpRHS == Cases[1].CmpRHS) || in shouldEmitAsBranches()
555 (Cases[0].CmpRHS == Cases[1].CmpLHS && in shouldEmitAsBranches()
556 Cases[0].CmpLHS == Cases[1].CmpRHS)) { in shouldEmitAsBranches()
562 if (Cases[0].CmpRHS == Cases[1].CmpRHS && in shouldEmitAsBranches()
563 Cases[0].PredInfo.Pred == Cases[1].PredInfo.Pred && in shouldEmitAsBranches()
564 isa<Constant>(Cases[0].CmpRHS) && in shouldEmitAsBranches()
565 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { in shouldEmitAsBranches()
566 if (Cases[0].PredInfo.Pred == CmpInst::ICMP_EQ && in shouldEmitAsBranches()
567 Cases[0].TrueBB == Cases[1].ThisBB) in shouldEmitAsBranches()
569 if (Cases[0].PredInfo.Pred == CmpInst::ICMP_NE && in shouldEmitAsBranches()
570 Cases[0].FalseBB == Cases[1].ThisBB) in shouldEmitAsBranches()
1103 for (unsigned I = 0, E = B.Cases.size(); I != E; ++I) { in emitBitTestHeader()
1104 if (!isUIntN(SwitchOpTy.getSizeInBits(), B.Cases[I].Mask)) { in emitBitTestHeader()
1119 MachineBasicBlock *MBB = B.Cases[0].ThisBB; in emitBitTestHeader()
1211 for (BitTestCase &BTC : BTB->Cases) in lowerBitTestWorkItem()
3573 for (unsigned j = 0, ej = BTB.Cases.size(); j != ej; ++j) { in finalizeBasicBlock()
3574 UnhandledProb -= BTB.Cases[j].ExtraProb; in finalizeBasicBlock()
3576 MachineBasicBlock *MBB = BTB.Cases[j].ThisBB; in finalizeBasicBlock()
3589 NextMBB = BTB.Cases[j + 1].TargetBB; in finalizeBasicBlock()
3595 NextMBB = BTB.Cases[j + 1].ThisBB; in finalizeBasicBlock()
3598 emitBitTestCase(BTB, NextMBB, UnhandledProb, BTB.Reg, BTB.Cases[j], MBB); in finalizeBasicBlock()
3605 BTB.Cases[ej - 1].TargetBB->getBasicBlock()}, in finalizeBasicBlock()
3608 BTB.Cases.pop_back(); in finalizeBasicBlock()
3618 addMachineCFGPred(HeaderToDefaultEdge, BTB.Cases.back().ThisBB); in finalizeBasicBlock()