Lines Matching refs:CCValAssign
656 SmallVector<CCValAssign, 16> ArgLocs; in determineAndHandleAssignments()
693 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
724 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
738 SmallVectorImpl<CCValAssign> &ArgLocs, in handleAssignments()
764 CCValAssign &VA = ArgLocs[j]; in handleAssignments()
807 if (VA.getLocInfo() == CCValAssign::Indirect) { in handleAssignments()
824 VA.getLocInfo() != CCValAssign::Indirect) { in handleAssignments()
833 assert((VA.getLocInfo() != CCValAssign::Indirect || Part == 0) && in handleAssignments()
839 CCValAssign &VA = ArgLocs[j + Idx]; in handleAssignments()
854 if (VA.getLocInfo() == CCValAssign::Indirect && in handleAssignments()
885 Handler.getStackAddress(VA.getLocInfo() == CCValAssign::Indirect in handleAssignments()
894 if (VA.getLocInfo() == CCValAssign::Indirect) in handleAssignments()
952 if (VA.getLocInfo() == CCValAssign::Indirect && in handleAssignments()
1100 if (Fn(I, VT, VT, CCValAssign::Full, Outs[I].Flags[0], CCInfo)) in checkReturn()
1142 const SmallVectorImpl<CCValAssign> &OutLocs, in parametersInCSRMatch()
1204 SmallVector<CCValAssign, 16> ArgLocs1; in resultsCompatible()
1209 SmallVector<CCValAssign, 16> ArgLocs2; in resultsCompatible()
1221 const CCValAssign &Loc1 = ArgLocs1[i]; in resultsCompatible()
1222 const CCValAssign &Loc2 = ArgLocs2[i]; in resultsCompatible()
1247 const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const { in getStackValueStoreType()
1273 CCValAssign &VA) const { in copyArgumentMemory()
1293 const CCValAssign &VA, in extendRegister()
1318 case CCValAssign::Full: in extendRegister()
1319 case CCValAssign::BCvt: in extendRegister()
1323 case CCValAssign::AExt: { in extendRegister()
1327 case CCValAssign::SExt: { in extendRegister()
1332 case CCValAssign::ZExt: { in extendRegister()
1344 const CCValAssign &VA, Register SrcReg, LLT NarrowTy) { in buildExtensionHint()
1346 case CCValAssign::LocInfo::ZExt: { in buildExtensionHint()
1352 case CCValAssign::LocInfo::SExt: { in buildExtensionHint()
1385 Register ValVReg, Register PhysReg, const CCValAssign &VA) { in assignValueToReg()