Lines Matching refs:UsedLanes

109                                              LaneBitmask UsedLanes) {  in addUsedLanesOnOperand()  argument
118 UsedLanes = TRI->composeSubRegIndexLaneMask(MOSubReg, UsedLanes); in addUsedLanesOnOperand()
119 UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg); in addUsedLanesOnOperand()
123 LaneBitmask PrevUsedLanes = MORegInfo.UsedLanes; in addUsedLanesOnOperand()
125 if ((UsedLanes & ~PrevUsedLanes).none()) in addUsedLanesOnOperand()
129 MORegInfo.UsedLanes = PrevUsedLanes | UsedLanes; in addUsedLanesOnOperand()
135 LaneBitmask UsedLanes) { in transferUsedLanesStep() argument
139 LaneBitmask UsedOnMO = transferUsedLanes(MI, UsedLanes, MO); in transferUsedLanesStep()
146 LaneBitmask UsedLanes, in transferUsedLanes() argument
155 return UsedLanes; in transferUsedLanes()
159 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
164 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
173 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx); in transferUsedLanes()
183 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
334 LaneBitmask UsedLanes = LaneBitmask::getNone(); in determineInitialUsedLanes() local
369 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
371 return UsedLanes; in determineInitialUsedLanes()
421 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none(); in isUndefRegAtInput()
441 LaneBitmask UsedLanes = DLD.transferUsedLanes(MI, DefRegInfo.UsedLanes, MO); in isUndefInput() local
442 if (UsedLanes.any()) in isUndefInput()
462 Info.UsedLanes = determineInitialUsedLanes(Reg); in computeSubRegisterLaneBitInfo()
476 transferUsedLanesStep(MI, Info.UsedLanes); in computeSubRegisterLaneBitInfo()
488 << " Used: " << PrintLaneMask(Info.UsedLanes) in computeSubRegisterLaneBitInfo()
511 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) { in modifySubRegisterOperandStatus()