Lines Matching full:mo
70 const MachineOperand &MO) { in isCrossCopy() argument
72 Register SrcReg = MO.getReg(); in isCrossCopy()
77 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
83 if (MO.getOperandNo() == 2) in isCrossCopy()
87 unsigned OpNum = MO.getOperandNo(); in isCrossCopy()
108 void DeadLaneDetector::addUsedLanesOnOperand(const MachineOperand &MO, in addUsedLanesOnOperand() argument
110 if (!MO.readsReg()) in addUsedLanesOnOperand()
112 Register MOReg = MO.getReg(); in addUsedLanesOnOperand()
116 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
136 for (const MachineOperand &MO : MI.uses()) { in transferUsedLanesStep() local
137 if (!MO.isReg() || !MO.getReg().isVirtual()) in transferUsedLanesStep()
139 LaneBitmask UsedOnMO = transferUsedLanes(MI, UsedLanes, MO); in transferUsedLanesStep()
140 addUsedLanesOnOperand(MO, UsedOnMO); in transferUsedLanesStep()
147 const MachineOperand &MO) const { in transferUsedLanes()
148 unsigned OpNum = MO.getOperandNo(); in transferUsedLanes()
293 for (const MachineOperand &MO : DefMI.uses()) { in determineInitialDefinedLanes() local
294 if (!MO.isReg() || !MO.readsReg()) in determineInitialDefinedLanes()
296 Register MOReg = MO.getReg(); in determineInitialDefinedLanes()
303 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) { in determineInitialDefinedLanes()
314 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
320 unsigned OpNum = MO.getOperandNo(); in determineInitialDefinedLanes()
335 for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { in determineInitialUsedLanes() local
336 if (!MO.readsReg()) in determineInitialUsedLanes()
339 const MachineInstr &UseMI = *MO.getParent(); in determineInitialUsedLanes()
343 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
355 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes()
400 bool isUndefRegAtInput(const MachineOperand &MO,
403 bool isUndefInput(const DeadLaneDetector &DLD, const MachineOperand &MO,
418 const MachineOperand &MO, const DeadLaneDetector::VRegInfo &RegInfo) const { in isUndefRegAtInput() argument
419 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
425 const MachineOperand &MO, in isUndefInput() argument
427 if (!MO.isUse()) in isUndefInput()
429 const MachineInstr &MI = *MO.getParent(); in isUndefInput()
441 LaneBitmask UsedLanes = DLD.transferUsedLanes(MI, DefRegInfo.UsedLanes, MO); in isUndefInput()
445 Register MOReg = MO.getReg(); in isUndefInput()
448 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO); in isUndefInput()
478 for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg)) in computeSubRegisterLaneBitInfo() local
479 transferDefinedLanesStep(MO, Info.DefinedLanes); in computeSubRegisterLaneBitInfo()
503 for (MachineOperand &MO : MI.operands()) { in modifySubRegisterOperandStatus()
504 if (!MO.isReg()) in modifySubRegisterOperandStatus()
506 Register Reg = MO.getReg(); in modifySubRegisterOperandStatus()
511 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) { in modifySubRegisterOperandStatus()
513 << "Marking operand '" << MO << "' as dead in " << MI); in modifySubRegisterOperandStatus()
514 MO.setIsDead(); in modifySubRegisterOperandStatus()
517 if (MO.readsReg()) { in modifySubRegisterOperandStatus()
519 if (isUndefRegAtInput(MO, RegInfo)) { in modifySubRegisterOperandStatus()
521 << "Marking operand '" << MO << "' as undef in " << MI); in modifySubRegisterOperandStatus()
522 MO.setIsUndef(); in modifySubRegisterOperandStatus()
524 } else if (isUndefInput(DLD, MO, &CrossCopy)) { in modifySubRegisterOperandStatus()
526 << "Marking operand '" << MO << "' as undef in " << MI); in modifySubRegisterOperandStatus()
527 MO.setIsUndef(); in modifySubRegisterOperandStatus()