Lines Matching refs:AddrSpace
733 unsigned AddrSpace = 0, Instruction *I = nullptr,
839 bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const;
853 unsigned AddrSpace = 0) const;
1643 unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
1653 unsigned AddrSpace) const;
1657 unsigned AddrSpace) const;
1888 int64_t Scale, unsigned AddrSpace,
1924 virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0;
1929 unsigned AddrSpace) = 0;
2153 virtual unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const = 0;
2158 unsigned AddrSpace) const = 0;
2161 unsigned AddrSpace) const = 0;
2361 bool HasBaseReg, int64_t Scale, unsigned AddrSpace, in isLegalAddressingMode() argument
2364 AddrSpace, I, ScalableOffset); in isLegalAddressingMode()
2445 bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) override { in hasVolatileVariant() argument
2446 return Impl.hasVolatileVariant(I, AddrSpace); in hasVolatileVariant()
2454 unsigned AddrSpace) override { in getScalingFactorCost() argument
2456 AddrSpace); in getScalingFactorCost()
2874 unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override { in getLoadStoreVecRegBitWidth() argument
2875 return Impl.getLoadStoreVecRegBitWidth(AddrSpace); in getLoadStoreVecRegBitWidth()
2884 unsigned AddrSpace) const override { in isLegalToVectorizeLoadChain() argument
2886 AddrSpace); in isLegalToVectorizeLoadChain()
2889 unsigned AddrSpace) const override { in isLegalToVectorizeStoreChain() argument
2891 AddrSpace); in isLegalToVectorizeStoreChain()