9 // Cortex-a8 erratum 657417 "A 32bit branch instruction that spans 2 4K regions
38 // "A 32bit branch instruction that spans two 4K regions can result in an
44 // xxxxxxffe f7fe // First halfword of branch to target:
46 // xxxxxx002 bfff // Second halfword of branch to target:
49 // - There is a 32-bit Thumb-2 branch instruction with an address of the form
52 // - The branch instruction is one of BLX, BL, B.w BCC.w
53 // - The instruction preceding the branch is a 32-bit non-branch instruction.
54 // - The target of the branch is in region 1.
56 // The linker mitigation for the fix is to redirect any branch that meets the
57 // erratum conditions to a patch section containing a branch to the target.
64 // 00000FFE       B.W func   // 32-bit branch spanning 2 regions, dest in 1st.
79   // Get the virtual address of the branch instruction at patcheeOffset.
92   // A decoding of the branch instruction at patcheeOffset.
116 // op1 == 0x0 op != x111xxx | Conditional branch (Bcc.W)
117 // op1 == 0x1               | Branch (B.W)
118 // op1 == 1x0               | Branch with Link and Exchange (BLX.w)
119 // op1 == 1x1               | Branch with Link (BL.W)
152 // Given a branch instruction instr at sourceAddr work out its destination
153 // address. This is only used when the branch instruction has no relocation.
178   // The base instruction of the patch is always a 32-bit unconditional branch.  in writeTo()
191   // Get the destination offset from the addend in the branch instruction.  in writeTo()
195   // A BLX changes the state of the branch in the patch to Arm state, which  in writeTo()
196   // has a PC Bias of 8, whereas in all other cases the branch is in Thumb  in writeTo()
203 // Given a branch instruction spanning two 4KiB regions, at offset off from the
204 // start of isec, return true if the destination of the branch is within the
211   // If there is a branch relocation at the same offset we must use this to  in branchDestInFirstRegion()
212   // find the destination address as the branch could be indirected via a thunk  in branchDestInFirstRegion()
219     // If there is no relocation, we must have an intra-section branch  in branchDestInFirstRegion()
227 // Return true if a branch can reach a patch section placed after isec.
232   // We need the branch at source to reach a patch section placed immediately  in patchInRange()
234   // add 0x100 as contingency to account for worst case of 1 branch every 4KiB  in patchInRange()
242   // Offset of branch within its InputSection.
244   // Cached decoding of the branch instruction.
246   // Branch relocation at off. Will be nullptr if no relocation exists.
250 // Detect the erratum sequence, returning the offset of the branch instruction
251 // and a decoding of the branch. If the erratum sequence is not found then
252 // return an offset of 0 for the branch. 0 is a safe value to use for no patch
253 // as there must be at least one 32-bit non-branch instruction before the
254 // branch so the minimum offset for a patch is 4.
259   // need to check for a 32-bit instruction immediately before a 32-bit branch  in scanCortexA8Errata657417()
281       // Find a relocation for the branch if it exists. This will be used  in scanCortexA8Errata657417()
373   // range of the Thumb-2 conditional branch with a contingency accounting for  in insertPatches()
408 // Given a branch instruction described by ScanRes redirect it to a patch
409 // section containing an unconditional branch instruction to the target.
410 // Ensure that this patch section is 4-byte aligned so that the branch cannot
412 // isec so the branch we are patching always goes forwards.
421   // unconditional branch in the patch must have a relocation so that any  in implementPatch()
434     // Create a branch relocation for the unconditional branch in the patch.  in implementPatch()
440       // The final target of the branch may be ARM or Thumb, if the target  in implementPatch()
456     // Redirect the existing branch relocation to the patch.  in implementPatch()