Lines Matching +full:- +full:4
1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 #define FROM_0_TO_15 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
14 #define FROM_0_TO_31 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,2…
32 # +-----------------------+
34 # +-----------------------+
36 # +-----------------------+ <-- SP
44 movl %ebx, 4(%eax)
55 movl 4(%esp), %edx
137 # thread_state pointer is in a0 ($4)
144 sw $1, (4 * 1)($4)
145 sw $2, (4 * 2)($4)
146 sw $3, (4 * 3)($4)
147 sw $4, (4 * 4)($4)
148 sw $5, (4 * 5)($4)
149 sw $6, (4 * 6)($4)
150 sw $7, (4 * 7)($4)
151 sw $8, (4 * 8)($4)
152 sw $9, (4 * 9)($4)
153 sw $10, (4 * 10)($4)
154 sw $11, (4 * 11)($4)
155 sw $12, (4 * 12)($4)
156 sw $13, (4 * 13)($4)
157 sw $14, (4 * 14)($4)
158 sw $15, (4 * 15)($4)
159 sw $16, (4 * 16)($4)
160 sw $17, (4 * 17)($4)
161 sw $18, (4 * 18)($4)
162 sw $19, (4 * 19)($4)
163 sw $20, (4 * 20)($4)
164 sw $21, (4 * 21)($4)
165 sw $22, (4 * 22)($4)
166 sw $23, (4 * 23)($4)
167 sw $24, (4 * 24)($4)
168 sw $25, (4 * 25)($4)
169 sw $26, (4 * 26)($4)
170 sw $27, (4 * 27)($4)
171 sw $28, (4 * 28)($4)
172 sw $29, (4 * 29)($4)
173 sw $30, (4 * 30)($4)
174 sw $31, (4 * 31)($4)
176 sw $31, (4 * 32)($4)
180 sw $8, (4 * 33)($4)
182 sw $8, (4 * 34)($4)
186 sdc1 $f0, (4 * 36 + 8 * 0)($4)
187 sdc1 $f2, (4 * 36 + 8 * 2)($4)
188 sdc1 $f4, (4 * 36 + 8 * 4)($4)
189 sdc1 $f6, (4 * 36 + 8 * 6)($4)
190 sdc1 $f8, (4 * 36 + 8 * 8)($4)
191 sdc1 $f10, (4 * 36 + 8 * 10)($4)
192 sdc1 $f12, (4 * 36 + 8 * 12)($4)
193 sdc1 $f14, (4 * 36 + 8 * 14)($4)
194 sdc1 $f16, (4 * 36 + 8 * 16)($4)
195 sdc1 $f18, (4 * 36 + 8 * 18)($4)
196 sdc1 $f20, (4 * 36 + 8 * 20)($4)
197 sdc1 $f22, (4 * 36 + 8 * 22)($4)
198 sdc1 $f24, (4 * 36 + 8 * 24)($4)
199 sdc1 $f26, (4 * 36 + 8 * 26)($4)
200 sdc1 $f28, (4 * 36 + 8 * 28)($4)
201 sdc1 $f30, (4 * 36 + 8 * 30)($4)
203 sdc1 $f0, (4 * 36 + 8 * 0)($4)
204 sdc1 $f1, (4 * 36 + 8 * 1)($4)
205 sdc1 $f2, (4 * 36 + 8 * 2)($4)
206 sdc1 $f3, (4 * 36 + 8 * 3)($4)
207 sdc1 $f4, (4 * 36 + 8 * 4)($4)
208 sdc1 $f5, (4 * 36 + 8 * 5)($4)
209 sdc1 $f6, (4 * 36 + 8 * 6)($4)
210 sdc1 $f7, (4 * 36 + 8 * 7)($4)
211 sdc1 $f8, (4 * 36 + 8 * 8)($4)
212 sdc1 $f9, (4 * 36 + 8 * 9)($4)
213 sdc1 $f10, (4 * 36 + 8 * 10)($4)
214 sdc1 $f11, (4 * 36 + 8 * 11)($4)
215 sdc1 $f12, (4 * 36 + 8 * 12)($4)
216 sdc1 $f13, (4 * 36 + 8 * 13)($4)
217 sdc1 $f14, (4 * 36 + 8 * 14)($4)
218 sdc1 $f15, (4 * 36 + 8 * 15)($4)
219 sdc1 $f16, (4 * 36 + 8 * 16)($4)
220 sdc1 $f17, (4 * 36 + 8 * 17)($4)
221 sdc1 $f18, (4 * 36 + 8 * 18)($4)
222 sdc1 $f19, (4 * 36 + 8 * 19)($4)
223 sdc1 $f20, (4 * 36 + 8 * 20)($4)
224 sdc1 $f21, (4 * 36 + 8 * 21)($4)
225 sdc1 $f22, (4 * 36 + 8 * 22)($4)
226 sdc1 $f23, (4 * 36 + 8 * 23)($4)
227 sdc1 $f24, (4 * 36 + 8 * 24)($4)
228 sdc1 $f25, (4 * 36 + 8 * 25)($4)
229 sdc1 $f26, (4 * 36 + 8 * 26)($4)
230 sdc1 $f27, (4 * 36 + 8 * 27)($4)
231 sdc1 $f28, (4 * 36 + 8 * 28)($4)
232 sdc1 $f29, (4 * 36 + 8 * 29)($4)
233 sdc1 $f30, (4 * 36 + 8 * 30)($4)
234 sdc1 $f31, (4 * 36 + 8 * 31)($4)
248 # thread_state pointer is in a0 ($4)
255 .irp i,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
256 sd $\i, (8 * \i)($4)
259 sd $31, (8 * 32)($4)
263 sd $8, (8 * 33)($4)
265 sd $8, (8 * 34)($4)
269 sdc1 $f\i, (280+8*\i)($4)
308 PPC64_STR(4) // Save r4 first since it will be used for fixing r2.
313 mflr 4
314 lwz 4, 0(4) // Get the first instruction at the return address.
315 xoris 0, 4, 0xe841 // Is it reloading the TOC register "ld 2,40(1)"?
372 addi 4, 3, PPC64_OFFS_FP
376 // For little-endian targets, we need a swap since stxvd2x will store the
379 // this can be changed to simply `stxv n, 16 * n(4)`.
382 stxvd2x n, 0, 4 ;\
383 addi 4, 4, 16
386 stxvd2x n, 0, 4 ;\
387 addi 4, 4, 16
394 PPC64_STVS(4)
466 PPC64_STF(4)
498 // Use 16-bytes below the stack pointer as an
500 // Note that the stack pointer is always 16-byte aligned.
501 subi 4, 1, 16
504 stvx n, 0, 4 ;\
505 ld 5, 0(4) ;\
507 ld 5, 8(4) ;\
514 PPC64_STV_UNALIGNED(4)
567 stw 4, 24(3) // Save r4 first since it will be used for fixing r2.
572 mflr 4
573 lwz 4, 0(4) // Get the instruction at the return address.
574 xoris 0, 4, 0x8041 // Is it reloading the TOC register "lwz 2,20(1)"?
633 stfd 4, 192(3)
666 subi 4, 1, 16
667 rlwinm 4, 4, 0, 0, 27 // mask low 4-bits
668 // r4 is now a 16-byte aligned pointer into the red zone
671 stvx _vec, 0, 4 SEPARATOR \
672 lwz 5, 0(4) SEPARATOR \
674 lwz 5, 4(4) SEPARATOR \
675 stw 5, _offset+4(3) SEPARATOR \
676 lwz 5, 8(4) SEPARATOR \
678 lwz 5, 12(4) SEPARATOR \
685 SAVE_VECTOR_UNALIGNED( 4, 424+0x040)
793 stm r0!, {r0-r7}
797 stm r0!, {r1-r3}
802 @ r12 does not need storing, it it the intra-procedure-call scratch register
806 @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
811 @ 32bit thumb-2 restrictions for stm:
814 stm r0, {r0-r12}
830 .fpu vfpv3-d16
833 vstmia r0, {d0-d15}
844 .fpu vfpv3-d16
847 vstmia r0, {d0-d15} @ fstmiax is deprecated in ARMv7+ and now behaves like vstmia
868 vstmia r0, {d16-d31}
913 stc2 p1, cr8, [r0], #4 @ wstrw wCGR0, [r0], #4
914 stc2 p1, cr9, [r0], #4 @ wstrw wCGR1, [r0], #4
915 stc2 p1, cr10, [r0], #4 @ wstrw wCGR2, [r0], #4
916 stc2 p1, cr11, [r0], #4 @ wstrw wCGR3, [r0], #4
931 l.sw 4(r3), r1
974 #define OFFSET(offset) (offset/4)
1060 save %sp, -176, %sp
1111 .irp i,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
1162 .irp i,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31