Lines Matching +full:8 +full:- +full:n +full:- +full:1
1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 #define FROM_0_TO_15 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
14 #define FROM_0_TO_31 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,2…
32 # +-----------------------+
34 # +-----------------------+
36 # +-----------------------+ <-- SP
43 subl $8,%edx
52 movl 8(%eax), %ecx
93 movq %rbx, 8(%rax)
96 movq 8(%rdi), %rbx
151 #define PPC64_LR(n) \ argument
152 ld n, (8 * (n + 2))(3)
163 PPC64_LR(8)
198 // For little-endian targets, we need a swap since lxvd2x will load the register
201 // this can be changed to simply `lxv n, (16 * n)(4)`.
202 #define PPC64_LVS(n) \ argument
203 lxvd2x n, 0, 4 ;\
204 xxswapd n, n ;\
207 #define PPC64_LVS(n) \ argument
208 lxvd2x n, 0, 4 ;\
214 PPC64_LVS(1)
221 PPC64_LVS(8)
247 #define PPC64_CLVS_RESTORE(n) \ argument
248 addi 4, 3, PPC64_OFFS_FP + n * 16 ;\
249 lxvd2x n, 0, 4 ;\
250 xxswapd n, n
252 #define PPC64_CLVS_RESTORE(n) \ argument
253 addi 4, 3, PPC64_OFFS_FP + n * 16 ;\
254 lxvd2x n, 0, 4
265 #define PPC64_CLVSl(n) \ argument
266 andis. 0, 5, (1 PPC_LEFT_SHIFT(47-n)) ;\
267 beq Ldone##n ;\
268 PPC64_CLVS_RESTORE(n) ;\
269 Ldone##n:
271 #define PPC64_CLVSh(n) \ argument
272 andi. 0, 5, (1 PPC_LEFT_SHIFT(63-n)) ;\
273 beq Ldone##n ;\
274 PPC64_CLVS_RESTORE(n) ;\
275 Ldone##n:
279 #define PPC64_CLVSl(n) PPC64_CLVS_RESTORE(n) argument
280 #define PPC64_CLVSh(n) PPC64_CLVS_RESTORE(n) argument
320 #define PPC64_LF(n) \ argument
321 lfd n, (PPC64_OFFS_FP + n * 16)(3)
325 PPC64_LF(1)
332 PPC64_LF(8)
359 #define PPC64_CLV_UNALIGNED_RESTORE(n) \ argument
360 ld 0, (PPC64_OFFS_V + n * 16)(3) ;\
362 ld 0, (PPC64_OFFS_V + n * 16 + 8)(3) ;\
363 std 0, 8(4) ;\
364 lvx n, 0, 4
373 #define PPC64_CLV_UNALIGNEDl(n) \ argument
374 andis. 0, 5, (1 PPC_LEFT_SHIFT(15-n)) ;\
375 beq Ldone##n ;\
376 PPC64_CLV_UNALIGNED_RESTORE(n) ;\
377 Ldone ## n:
379 #define PPC64_CLV_UNALIGNEDh(n) \ argument
380 andi. 0, 5, (1 PPC_LEFT_SHIFT(31-n)) ;\
381 beq Ldone##n ;\
382 PPC64_CLV_UNALIGNED_RESTORE(n) ;\
383 Ldone ## n:
387 #define PPC64_CLV_UNALIGNEDl(n) PPC64_CLV_UNALIGNED_RESTORE(n) argument
388 #define PPC64_CLV_UNALIGNEDh(n) PPC64_CLV_UNALIGNED_RESTORE(n) argument
392 subi 4, 1, 16
393 // r4 is now a 16-byte aligned pointer into the red zone
394 // the _vectorScalarRegisters may not be 16-byte aligned
398 PPC64_CLV_UNALIGNEDl(1)
405 PPC64_CLV_UNALIGNEDl(8)
444 ld 0, (8 * (3 + 2))(3)
450 PPC64_LR(1)
477 lwz 8, 40(3)
505 lfd 1, 168(3)
512 lfd 8, 224(3)
545 lwz 0, 424+_index*16+8(3) SEPARATOR \
546 stw 0, 8(4) SEPARATOR \
559 andis. 0, 5, (1 PPC_LEFT_SHIFT(15-_index)) SEPARATOR \
565 andi. 0, 5, (1 PPC_LEFT_SHIFT(31-_index)) SEPARATOR \
577 subi 4, 1, 16
578 rlwinm 4, 4, 0, 0, 27 // mask low 4-bits
579 // r4 is now a 16-byte aligned pointer into the red zone
580 // the _vectorRegisters may not be 16-byte aligned so copy via red zone temp buffer
583 LOAD_VECTOR_UNALIGNEDl(1)
590 LOAD_VECTOR_UNALIGNEDl(8)
623 lwz 0, 8(3) // do r0 now
626 lwz 1, 12(3) // do sp now
682 // could clobber the de-allocated portion of the stack after sp has been
691 mov x16, #1
716 #if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
717 @ r8-r11: ldm into r1-r4, then mov to r8-r11
719 ldm r0!, {r1-r4}
725 @ r12 does not need loading, it it the intra-procedure-call scratch register
730 ldm r0, {r0-r7}
734 @ 32bit thumb-2 restrictions for ldm:
737 ldm lr, {r0-r12}
757 .fpu vfpv3-d16
767 vldmia r0, {d0-d15}
778 .fpu vfpv3-d16
781 vldmia r0, {d0-d15} @ fldmiax is deprecated in ARMv7+ and now behaves like vldmia
795 vldmia r0, {d16-d31}
811 ldcl p1, cr0, [r0], #8 @ wldrd wR0, [r0], #8
812 ldcl p1, cr1, [r0], #8 @ wldrd wR1, [r0], #8
813 ldcl p1, cr2, [r0], #8 @ wldrd wR2, [r0], #8
814 ldcl p1, cr3, [r0], #8 @ wldrd wR3, [r0], #8
815 ldcl p1, cr4, [r0], #8 @ wldrd wR4, [r0], #8
816 ldcl p1, cr5, [r0], #8 @ wldrd wR5, [r0], #8
817 ldcl p1, cr6, [r0], #8 @ wldrd wR6, [r0], #8
818 ldcl p1, cr7, [r0], #8 @ wldrd wR7, [r0], #8
819 ldcl p1, cr8, [r0], #8 @ wldrd wR8, [r0], #8
820 ldcl p1, cr9, [r0], #8 @ wldrd wR9, [r0], #8
821 ldcl p1, cr10, [r0], #8 @ wldrd wR10, [r0], #8
822 ldcl p1, cr11, [r0], #8 @ wldrd wR11, [r0], #8
823 ldcl p1, cr12, [r0], #8 @ wldrd wR12, [r0], #8
824 ldcl p1, cr13, [r0], #8 @ wldrd wR13, [r0], #8
825 ldcl p1, cr14, [r0], #8 @ wldrd wR14, [r0], #8
826 ldcl p1, cr15, [r0], #8 @ wldrd wR15, [r0], #8
861 l.lwz r2, 8(r3)
959 ldc1 $f0, (4 * 36 + 8 * 0)($4)
960 ldc1 $f2, (4 * 36 + 8 * 2)($4)
961 ldc1 $f4, (4 * 36 + 8 * 4)($4)
962 ldc1 $f6, (4 * 36 + 8 * 6)($4)
963 ldc1 $f8, (4 * 36 + 8 * 8)($4)
964 ldc1 $f10, (4 * 36 + 8 * 10)($4)
965 ldc1 $f12, (4 * 36 + 8 * 12)($4)
966 ldc1 $f14, (4 * 36 + 8 * 14)($4)
967 ldc1 $f16, (4 * 36 + 8 * 16)($4)
968 ldc1 $f18, (4 * 36 + 8 * 18)($4)
969 ldc1 $f20, (4 * 36 + 8 * 20)($4)
970 ldc1 $f22, (4 * 36 + 8 * 22)($4)
971 ldc1 $f24, (4 * 36 + 8 * 24)($4)
972 ldc1 $f26, (4 * 36 + 8 * 26)($4)
973 ldc1 $f28, (4 * 36 + 8 * 28)($4)
974 ldc1 $f30, (4 * 36 + 8 * 30)($4)
976 ldc1 $f0, (4 * 36 + 8 * 0)($4)
977 ldc1 $f1, (4 * 36 + 8 * 1)($4)
978 ldc1 $f2, (4 * 36 + 8 * 2)($4)
979 ldc1 $f3, (4 * 36 + 8 * 3)($4)
980 ldc1 $f4, (4 * 36 + 8 * 4)($4)
981 ldc1 $f5, (4 * 36 + 8 * 5)($4)
982 ldc1 $f6, (4 * 36 + 8 * 6)($4)
983 ldc1 $f7, (4 * 36 + 8 * 7)($4)
984 ldc1 $f8, (4 * 36 + 8 * 8)($4)
985 ldc1 $f9, (4 * 36 + 8 * 9)($4)
986 ldc1 $f10, (4 * 36 + 8 * 10)($4)
987 ldc1 $f11, (4 * 36 + 8 * 11)($4)
988 ldc1 $f12, (4 * 36 + 8 * 12)($4)
989 ldc1 $f13, (4 * 36 + 8 * 13)($4)
990 ldc1 $f14, (4 * 36 + 8 * 14)($4)
991 ldc1 $f15, (4 * 36 + 8 * 15)($4)
992 ldc1 $f16, (4 * 36 + 8 * 16)($4)
993 ldc1 $f17, (4 * 36 + 8 * 17)($4)
994 ldc1 $f18, (4 * 36 + 8 * 18)($4)
995 ldc1 $f19, (4 * 36 + 8 * 19)($4)
996 ldc1 $f20, (4 * 36 + 8 * 20)($4)
997 ldc1 $f21, (4 * 36 + 8 * 21)($4)
998 ldc1 $f22, (4 * 36 + 8 * 22)($4)
999 ldc1 $f23, (4 * 36 + 8 * 23)($4)
1000 ldc1 $f24, (4 * 36 + 8 * 24)($4)
1001 ldc1 $f25, (4 * 36 + 8 * 25)($4)
1002 ldc1 $f26, (4 * 36 + 8 * 26)($4)
1003 ldc1 $f27, (4 * 36 + 8 * 27)($4)
1004 ldc1 $f28, (4 * 36 + 8 * 28)($4)
1005 ldc1 $f29, (4 * 36 + 8 * 29)($4)
1006 ldc1 $f30, (4 * 36 + 8 * 30)($4)
1007 ldc1 $f31, (4 * 36 + 8 * 31)($4)
1012 lw $8, (4 * 33)($4)
1013 mthi $8
1014 lw $8, (4 * 34)($4)
1015 mtlo $8
1018 lw $1, (4 * 1)($4)
1025 lw $8, (4 * 8)($4)
1070 ldc1 $f\i, (280+8*\i)($4)
1075 ld $8, (8 * 33)($4)
1076 mthi $8
1077 ld $8, (8 * 34)($4)
1078 mtlo $8
1081 ld $1, (8 * 1)($4)
1082 ld $2, (8 * 2)($4)
1083 ld $3, (8 * 3)($4)
1085 .irp i,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
1086 ld $\i, (8 * \i)($4)
1089 ld $31, (8 * 32)($4)
1092 ld $4, (8 * 4)($4)
1182 .irp i,2,3,4,5,6,7,8,9
1204 lg %r1, 8(%r2)
1208 ld %f\i, (144+8*\i)(%r2)
1211 // Restore GPRs - skipping %r0 and %r1
1229 fld.d $f\i, $a0, (8 * 33 + 8 * \i)
1234 .irp i,1,2,3
1235 ld.d $r\i, $a0, (8 * \i)
1238 .irp i,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
1239 ld.d $r\i, $a0, (8 * \i)
1242 ld.d $ra, $a0, (8 * 32) // load new pc into $ra
1243 ld.d $a0, $a0, (8 * 4) // restore $a0 last